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componentes Descripción

Fabricante

DSP56303

DSP56303 24-bit digital signal processor (DSP)

Freescale Semiconductor 

Signals/Connections

VCCP

VCCQ

VCCA

VCCD

VCCC

4

4

4

2

VCCH

VCCS

2

GNDP

GNDP1

GNDQ

GNDA

GNDD

4

4

4

2

GNDC

GNDH 2

GNDS

EXTAL

XTAL

DSP56303

Power Inputs:

PLL

Internal Logic

Interrupt/

Mode

Control

Address Bus

Data Bus

Bus Control

HI08

8

ESSI/SCI/Timer

Host

Grounds4:

PLL

Interface

(HI08) Port1

PLL

Internal Logic

Address Bus

Data Bus

Bus Control

HI08

ESSI/SCI/Timer

Clock

Enhanced 3

Synchronous Serial

Interface Port 0

(ESSI0)2

MODA/IRQA

MODB/IRQB

MODC/IRQC

MODD/IRQD

RESET

Non-Multiplexed Multiplexed

Bus

Bus

H[0–7]

HAD[0–7]

HA0

HAS/HAS

HA1

HA8

HA2

HA9

HCS/HCS

HA10

Single DS

Double DS

HRW

HRD/HRD

HDS/HDS

HWR/HWR

Single HR

Double HR

HREQ/HREQ HTRQ/HTRQ

HACK/HACK HRRQ/HRRQ

Port B

GPIO

PB[0–7]

PB8

PB9

PB10

PB13

PB11

PB12

PB14

PB15

SC0[0–2]

SCK0

SRD0

STD0

Port C GPIO

PC[0–2]

PC3

PC4

PC5

CLKOUT

PCAP

PLL

PINIT/NMI

Port A

A[0–17] 18 External

Address Bus

D[0–23] 24 External

Data Bus

AA0/RAS0–

AA3/RAS3

RD

WR

TA

BR

BG

BB

CAS

BCLK

BCLK

4

External

Bus

Control

Enhanced 3

Synchronous Serial

Interface Port 1

(ESSI1)2

SC1[0–2]

SCK1

SRD1

STD1

Serial

Communications

Interface (SCI) Port2

RXD

TXD

SCLK

Timers3

JTAG/OnCE

Port

TIO0

TIO1

TIO2

TCK

TDI

TDO

TMS

TRST

DE

Port D GPIO

PD[0–2]

PD3

PD4

PD5

Port E GPIO

PE0

PE1

PE2

Timer GPIO

TIO0

TIO1

TIO2

Note:

1. The HI08 port supports a non-multiplexed or a multiplexed bus, single or double Data Strobe (DS), and single or

double Host Request (HR) configurations. Since each mode is configured independently, any combination of these

modes is possible. These HI08 signals can also be configured as GPIO signals (PB[0–15]). Signals with dual

designations (for example, HAS/HAS) have configurable polarity.

2. The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals

(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.

3. TIO[0–2] can be configured as GPIO signals.

4. The GND signals are listed for the 144-pin TQFP package. For the 196-ball MAP-BGA package, all grounds except

GNDP and GNDP1 are connected toegether and referenced as GND. There are 64 GND connections.

Figure 2-1. Signals Identified by Functional Group

DSP56303 User’s Manual, Rev. 2

2-2

Freescale Semiconductor

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