DS75LV Ver la hoja de datos (PDF) - Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

DS75LV

Digital Thermometer and Thermostat

Maxim Integrated 

DS75LV

Digital Thermometer and Thermostat

AC Electrical Characteristics (continued)

(1.7V ≤ VDD ≤ 3.7V, TA = -55°C to +125°C, unless otherwise noted.)

PARAMETER

Low Period of SCL

High Period of SCL

Repeated START Condition

Setup Time to Rising SCL

SYMBOL

tLOW

tHIGH

tSU:STA

(Note 5)

(Note 5)

(Note 5)

CONDITIONS

MIN

TYP

MAX UNITS

1.3

µs

0.6

µs

600

ns

Data-Out Hold Time from

Falling SCL

tHD:DAT (Notes 5, 7)

0

0.9

µs

Data-In Setup Time to Rising

SCL

tSU:DAT (Note 5)

100

ns

Rise Time of SDA and SCL

(Receive)

tR

(Note 5)

1000

ns

Fall Time of SDA and SCL

(Receive)

tF

(Note 5)

300

ns

Spike Suppression Filter Time

(Deglitch Filter)

tSS

0

50

ns

STOP Setup Time to Rising

SCL

tSU:STO (Note 5)

600

ns

Capacitive Load for Each Bus

Line

Input Capacitance

Serial Interface Reset Time

CB

CI

tTIMEOUT

SDA time low (Note 8)

400

pF

5

pF

75

325

ms

Note 1:

Note 2:

Note 3:

Note 4:

Note 5:

Note 6:

Note 7:

Note 8:

Internal heating caused by OS loading causes the DS75LV to read approximately 0.5°C higher if OS is sinking the max

rated current.

All voltages are referenced to ground.

IDD specified with VDD at 3.0V and SDA, SCL = 3.0V, 0°C to +70°C.

IDD specified with OS pin open.

See Figure 2 for timing diagram. All timing is referenced to 0.9 x VDD and 0.1 x VDD.

After this period, the first clock pulse is generated.

The DS75LV provides an internal hold time of at least 75ns on the SDA signal to bridge the undefined region of SCL’s

falling edge.

This timeout applies only when the DS75LV is holding SDA low. Other devices can hold SDA low indefinitely and the

DS75LV does not reset.

www.maximintegrated.com

Maxim Integrated │  3

Share Link: