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DS2703

SHA-1 Battery Pack Authentication IC

Dallas Semiconductor -> Maxim Integrated 

Table 1. Variable Initiation

[31:0]

[23:16]

A

67h

45h

B

EFh

CDh

C

98h

BAh

D

10h

32h

E

C3h

D2h

[15:8]

23h

ABh

DCh

54h

E1h

DS2703 SHA-1 Battery Pack Authentication IC

[7:0]

01h

89h

FEh

76h

F0h

The 160-bit MAC is computed per FIPS 180, including the addition of constants H0-H4. Adding H0-H4 is necessary

only to maintain compliance with FIPS 180. The computed MAC is held in the A-E register memory and then

returned as a 160-bit serial stream, beginning with the least significant bit of variable A.

Table 2. Message Authentication Code (MAC) Return Format

A[31:24]

B[31:24]

C[31:24]

D[31:24]

E[31:24]

A[23:16]

B[23:16]

C[23:16]

D[23:16]

E[23:16]

A[15:8]

B[15:8]

C[15:8]

D[15:8]

E[15:8]

A[7:0]

B[7:0]

C[7:0]

D[7:0]

E[7:0]

SHA-1 HASH ALGORITHM

General Definitions:

This description of the SHA computation is adapted from the Secure Hash Standard SHA-1 document. The

algorithm takes as its input data 16, 32-bit words Mt (0 ≤ t ≤ 15) as shown in the SHA-1 Input Message Format

tables. The SHA computation involves six 32-bit word variables labeled A, B, C, D, E, and TMP, five 32-bit word

constants labeled H0, H1, H2, H3, and H4, a sequence of eighty 32-bit words called Wt (0 ≤ t ≤ 79), a sequence of

eighty 32-bit words called Kt (0 ≤ t ≤ 79), and a Boolean function ft(B,C,D) (0 ≤ t ≤ 79). The operations required for

the SHA computation are arithmetic addition without carry ("+"), logical inversion or 1's complement ("\"), logical

XOR ("Å"), logical AND ("^"), logical OR ("v"), concatenation of 32-bit values (“|”), assignment (":=") and circular

shifting within a 32-bit word. The expression Sn(X) represents a circular shift of X by n positions to the left, with X

being a 32-bit word.

The function ft is defined as follows:

ft(B,C,D) = (B^C)v((B\)^D)

= BÅCÅD

= (B^C)v(B^D)v(C^D)

= BÅCÅD

(0 ≤ t ≤ 19)

(20 ≤ t ≤ 39)

(40 ≤ t ≤ 59)

(60 ≤ t ≤ 79)

The sequence Kt (0 ≤ t ≤ 79) is defined as follows:

Kt

:=

5A827999h

(0 ≤ t ≤ 19)

6ED9EBA1h

(20 ≤ t ≤ 39)

8F1BBCDCh

(40 ≤ t ≤ 59)

CA62C1D6h

(60 ≤ t ≤ 79)

The sequence Wt (0 ≤ t ≤ 79) is defined as follows:

Wt

:=

Mt (see table, FIPS-180 compliant input block) (0 ≤ t ≤ 15)

S1(Wt-3 Å Wt-8 Å Wt-14 Å Wt-16) (16 ≤ t ≤ 79)

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