DS2125(2004) Ver la hoja de datos (PDF) - Maxim Integrated
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DS2125 Datasheet PDF : 7 Pages
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DS2125 Ultra3 LVD/SE SCSI 15-Line Terminator
The DS2125’s DIFF_CAP pin monitors the DIFFSENS line to determine the device’s proper operating mode. The
DIFFSENSE pin can also drive the SCSI DIFFSENS line to determine the SCSI bus-operating mode. The DS2125
switches to the termination mode that is appropriate for the bus based on the value of the DIFFSENS voltage.
These modes are LVD mode, SE mode, and HVD isolation mode.
LVD MODE
A precision laser-trimmed resistor string with two amplifiers provides LVD termination. This configuration yields
105W differential and 150W common-mode impedance. A 112mV fail-safe bias is maintained when no drivers are
connected to the SCSI bus.
SE MODE
When the external driver for a given signal line turns off, the active terminator pulls that signal line to 2.85V
(quiescent state). The terminating resistors maintain their 110W value.
HVD ISOLATION MODE
The DS2125 identifies that there is an HVD device on the SCSI bus and isolates the termination pins from the bus.
When ISO is pulled high, the termination pins are isolated from the SCSI bus, and VREF remains active. During
thermal shutdown, the termination pins are isolated from the SCSI bus, and VREF becomes high impedance. The
DIFFSENSE driver is shut down during either of these two events. An internal pulldown resistor assures that the
DS2125 is terminating the bus if the ISO pin is left floating.
To ensure proper operation, the TPWR pin should be connected to the SCSI bus TERMPWR line. As with all
analog circuitry, the TERMPWR and VDD lines should be bypassed locally. A 2.2mF capacitor and a 0.01mF high-
frequency capacitor are recommended between TPWR and ground, and placed as close as possible to the
DS2125. The DS2125 should be placed as close as possible to the SCSI connector to minimize signal and power
trace length, thereby resulting in less input capacitance and reflections, which can degrade the bus signals.
To maintain the specified regulation, a 4.7mF capacitor is required between the VREF pin and ground of each
DS2125. A high-frequency capacitor (0.1mF ceramic recommended) can also be placed on the VREF pin in
applications that use fast rise/fall-time drivers. Figure 2 shows a typical SCSI bus configuration.
REFERENCE DOCUMENTS
TITLE
T10 PROJECT
DOCUMENT
SCSI Parallel Interface 2 (SPI-2) Project: 1142-M, 1998
SCSI Parallel Interface 3 (SPI-3) Project: 1302-D, 1999
SCSI Parallel Interface 4 (SPI-4) Project: 1365-D, 200x
T10 COMMITTEE FTP LINK
ftp://ftp.t10.org/t10/drafts/spi2/spi2r20b.pdf
ftp://ftp.t10.org/t10/drafts/spi3/spi3r14.pdf
ftp://ftp.t10.org/t10/drafts/spi4/spi4r10.pdf
ANSI
DOCUMENT NO.
X3.302:1998
NCITS.336:2000
INCITS.362:2002
SUPPLIERS
SUPPLIER
American National Standards Institute (ANSI)
Global Engineering Documents
PHONE
212-642-4900
800-854-7179
WEBSITE
www.ansi.org/
http://global.ihs.com/
CHIP INFORMATION
TRANSISTOR COUNT: 8382 MOS and 87 BiPOLAR
PROCESS: BiCMOS
SUBSTRATE CONNECTED TO GROUND
THERMAL INFORMATION
Theta-JA: 65°C/W
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