DS2227 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

Número de pieza

componentes Descripción

Fabricante

DS2227

Flexible NV SRAM Stik

Dallas Semiconductor -> Maxim Integrated 

NOTES:

1. WE is high for a read cycle.

DS2227

2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance

state.

3. tWP is specified as the logical AND of CE and WE .

4. tDH, tDS are measured from the earlier of CE or WE going high.

5. tDH is measured from WE going high. If CE is used to terminate the write cycle then tDH = 20 ns.

6. If the CE low transition occurs simultaneously with or later than the WE low transition, the

output buffers remain in a high impedance state in this period.

7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output

buffers remain in a high impedance state in this period.

8. If the WE is low or the WE low transition occurs prior to or simultaneously with the CE low

transition, the output buffers remain in a high impedance state in this period.

9. Each DS2227 is marked with a 4-digit date code AABB. AA designates the year of manufacture.

BB designates the week of manufacture. The minimum expected tDR is defined as starting at the

date of manufacture.

10. Timings are valid only when CE is tied low.

DC TEST CONDITIONS

Outputs Open

Cycle = 200 ns

All Voltages are Referenced to Ground

AC TEST CONDITIONS

Output Load: 100 pF + 1TTL gate

Input Pulse Levels: 0 - 3.0 V

Timing Measurements Reference Levels:

Input - 1.5V

Output - 1.5V

Input Pulse Rise and Fall Times: 5 ns

ORDERING INFORMATION

9 of 10

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