DS21372 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21372

3.3V Bit Error Rate Tester (BERT)

Dallas Semiconductor -> Maxim Integrated 

DS21372

2. PARALLEL CONTROL INTERFACE

The DS21372 is controlled via a multiplexed bi-directional address/data bus by an external

microcontroller or microprocessor. The DS21372 can operate with either Intel or Motorola bus timing

configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will

be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C.

Electrical Characteristics for more details. The multiplexed bus on the DS21372 saves pins because the

address information and data information share the same signal paths. The addresses are presented to the

pins in the first portion of the bus cycle and data will be transferred on the pins during second portion of

the bus cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS21372

latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during

the later portion of the DS or WR pulses. In a read cycle, the DS21372 outputs a byte of data during the

latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high

impedance state as RD transitions high in Intel timing or as DS transitions low in Motorola timing. The

DS21372 can also be easily connected to non-multiplexed buses. RCLK and TCLK are used to update

counters and load transmit and receive pattern registers. At slow clock rates, sufficient time must be

allowed for these port operations.

3. PATTERN SET REGISTERS

The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or

repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded

with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that is

to be repeated. Please see Tables 4 and 5 for some programming examples.

PATTERN SET REGISTERS

(MSB)

PS31 PS30 PS29 PS28 PS27

PS23 PS22 PS21 PS20 PS19

PS15 PS14 PS13 PS12 PS11

PS7 PS6 PS5 PS4 PS3

PS26

PS18

PS10

PS2

PS25

PS17

PS9

PS1

(LSB)

PS24

PS16

PS8

PS0

PSR3 (addr.=00 Hex)

PSR2 (addr.=01 Hex)

PSR1 (addr.=02 Hex)

PSR0 (addr.=03 Hex)

4. PATTERN LENGTH REGISTER

Length Bits LB4 to LB0 determine the length of the pseudorandom polynomial or programmable

repetitive pattern that is generated and detected. With the pseudorandom patterns, the “Tap A” feedback

position of the pattern generator is always equal to the value in the Pattern Length Register (PLR). Please

refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for some

programming examples.

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