DS21372 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21372

3.3V Bit Error Rate Tester (BERT)

Dallas Semiconductor -> Maxim Integrated 

DETAILED PIN DESCRIPTION Table 1

DS21372

PIN SYMBOL TYPE DESCRIPTION

1

TL

I Transmit Load. A positive-going edge loads the pattern generator with

the contents of the Pattern Set Registers. The MSB of the repetitive or

pseudorandom pattern appears at TDATA after the third positive edge of

TCLK from asserting TL. TL is logically OR’ed with PCR.7 and should

be tied to VSS if not used. See Figure 8 for timing information.

2

AD0

I/O Data Bus. An 8-bit multiplexed address/data bus.

3

AD1

I/O Data Bus. An 8-bit multiplexed address/data bus.

4

TEST

I Test. Set high to 3-state all output pins ( INT , ADx, TDATA, RLOS).

Should be tied to VSS to enable all outputs.

5

VSS

- Signal Ground. 0.0 volts. Should be tied to local ground plane.

6

AD2

I/O Data Bus. An 8-bit multiplexed address/data bus.

7

AD3

I/O Data Bus. An 8-bit multiplexed address/data bus.

8

AD4

I/O Data Bus. An 8-bit multiplexed address/data bus.

9

AD5

I/O Data Bus. An 8-bit multiplexed address/data bus.

10

AD6

I/O Data Bus. An 8-bit multiplexed address/data bus.

11

AD7

I/O Data Bus. An 8-bit multiplexed address/data bus.

12

VSS

13

VDD

14

BTS

- Signal Ground. 0.0 volts. Should be tied to local ground plane.

- Positive Supply. 3.3 volts.

I Bus Type Select. Strap high to select Motorola bus timing; strap low to

select Intel bus timing. This pin controls the function of the RD (DS),

ALE(AS), and WR (R/ W ) pins. If BTS = 1, then these pins assume the

function listed in parenthesis ().

15 RD (DS)

I Read Input (Data Strobe).

16

CS

I Chip Select. Must be low to read or write the port.

17 ALE(AS)

I Address Latch Enable (Address Strobe). A positive going edge serves

to demultiplex the bus.

18 WR (R/ W ) I Write Input (Read/Write).

19

INT

O Alarm Interrupt. Flags host controller during conditions defined in

Status Register. Active low, open drain output.

20

VDD

21

VSS

22

LC

23 RLOS

- Positive Supply. 3.3 volts.

- Signal Ground. 0.0 volts. Should be tied to local ground plane.

I Load Count. A positive-going edge latches the current bit and bit error

count into the user accessible BCR and BECR registers and clears the

internal count registers. LC is logically OR’ed with control bit PCR.4.

Should be tied to VSS if not used.

O Receive Loss Of Sync. Indicates the real time status of the receive

synchronizer. Active high output.

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