DS1994 Ver la hoja de datos (PDF) - Maxim Integrated

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DS1994

4Kb Plus Time Memory iButton®

Maxim Integrated 

DS1994

6 STOP/START Stop/Start (in manual mode)

If the interval timer is in manual mode, the interval timer starts counting when this bit is set to a logic 0

and stops counting when set to a logic 1. If the interval timer is in automatic mode, this bit has no effect.

7 DSEL Delay Select Bit

This bit selects the delay that it takes for the cycle counter and the interval timer (in auto mode) to see a

transition on the data line. When this bit is set to a logic 1, the delay time is 123  2ms. This delay allows

communication on the data line without starting or stopping the interval timer and without incrementing

the cycle counter. When this bit is set to a logic 0, the delay time is 3.5  0.5ms.

MEMORY FUNCTION COMMANDS

The Memory Function Flowchart (Figure 6) describes the protocols necessary for accessing the memory.

An example follows the flowchart. Three address registers are provided as shown in Figure 5. The first

two registers represent a 16-bit target address (TA1, TA2). The third register is the ending offset/data

status Byte (E/S).

The target address points to a unique Byte location in memory. The first 5 bits of the target address

(T4:T0) represent the Byte offset within a page. This Byte offset points to one of 32 possible Byte

locations within a given page. For instance, 00000b points to the first Byte of a page where as 11111b

would point to the last Byte of a page.

The third register (E/S) is a read only register. The first 5 bits (E4:E0) of this register are called the

ending offset. The ending offset is a Byte offset within a page (1 of 32 Bytes). Bit 5 (PF) is the partial

Byte flag. Bit 6 (OF) is the overflow flag. Bit 7 (AA) is the authorization accepted flag.

Figure 5. ADDRESS REGISTERS

TARGET ADDRESS (TA1)

7

6

5

4

3

2

1

0

T7 T6 T5 T4 T3 T2 T1 T0

TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8

ENDING ADDRESS WITH

DATA STATUS (E/S)

AA OF PF E4 E3 E2 E1 E0

(READ ONLY)

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