DS1846 Ver la hoja de datos (PDF) - Maxim Integrated
Número de pieza
componentes Descripción
Fabricante
DS1846 Datasheet PDF : 18 Pages
| |||
DS1846
DS1846 is not latched into EEPROM. Note that in order for eight bytes to be stored sequentially (and to
prevent looping around), the address byte must be set to the beginning of the desired page (three LSBs of
the address are 0). For detailed information concerning page operations, see the MEMORY
ORGANIZATION section.
The DS1846 is capable of an 8-byte page write. A page write is initiated the same way as a byte write, but
the master does not send a stop condition after the first data byte. Instead, after the slave acknowledges
receipt of the data byte, the master can send up to seven more data bytes using the same nine-clock
sequence. After a write to the last byte in the page, the address returns to the beginning of the page. The
master must terminate the write cycle with a stop condition or the data clocked into the DS1846 is not
latched into permanent memory.
Acknowledge Polling: Once the internally timed write has started and the DS1846 inputs are disabled,
acknowledge polling can be initiated. The process involves transmitting a start condition followed by the
device address. The R/W bit signifies the type of operation that is desired. The read or write sequence is
only allowed to proceed if the internal write cycle has completed and the DS1846 responds with a zero.
Read Operations: After receiving a matching address byte with the R/W bit set high, the device goes
into the read mode of operation. There are three read operations: current address read, random read, and
sequential address read.
CURRENT ADDRESS READ
The DS1846 has an internal address register that maintains the address used during the last read or write
operation, incremented by one. This data is maintained as long as VCC is valid. If the most recent address
was the last byte in memory, then the register resets to the first address. This address stays valid between
operations as long as power is available.
Once the device address is clocked in and acknowledged by the DS1846 with the R/W bit set to high, the
current address data word is clocked out. The master does not respond with a zero, but does generate a
stop condition afterwards.
RANDOM READ
A random read requires a dummy byte write sequence to load in the data word address. Once the device
address and data bytes are clocked in by the master, and acknowledged by the DS1846, the master must
generate another start condition. The master now initiates a current address read by sending the device
address with the R/W bit set high. The DS1846 acknowledges the device address and serially clocks out
the data byte.
SEQUENTIAL ADDRESS READ
Sequential reads are initiated by either a current address read or a random address read. After the master
receives the first data byte, the master responds with an acknowledge. As long as the DS1846 receives
this acknowledge after a byte is read, the master may clock out additional data words from the DS1846.
After reaching address FFh, it resets to address 00h.
The sequential read operation is terminated when the master initiates a stop condition. The master does
not respond with a zero.
For a more detailed description of 2-wire theory of operation, see the following section.
6 of 18
Share Link: 