DS1922L Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS1922L Datasheet PDF : 48 Pages
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DS1922L/DS1922T
I/O Pin, 1-Wire Read
Read Low Time
(Notes 1, 14)
Read Sample Time
(Notes 1, 14)
Real Time Clock
Accuracy
Frequency Deviation
Temperature Converter
Conversion Time
(Note 15)
Thermal Response Time
Constant (note 16)
Conv. Error Without
Software Correction (note
17)
Conv. Error With Software
Correction (Note 18)
tRL
tMSR
DF
tCONV
tRESP
DJ
DJ
Standard speed
Overdrive speed
Standard speed
Overdrive speed
+25°C
-40°C to +85°C
0°C to +125°C
8-bit mode
16-bit mode (11 bits)
iButton package
5
1
tRL + d
tRL + d
15 - d
1.95 - d
µs
15
1.95
µs
-2
-300
-600
+2
min/
month
+60
+60
PPM
30
240
75
600
ms
130
s
See Temperature Accuracy
Graphs
°C
See Temperature Accuracy
Graphs
°C
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
System Requirement
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2480B may be required.
Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2kW resistor is used to pull up the data line, 2.5µs
after VPUP has been applied the parasite capacitance will not affect normal communications.
VTL, VTH are a function of the internal supply voltage.
Voltage below which, during a falling edge on I/O, a logic '0' is detected.
The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low.
Voltage above which, during a rising edge on I/O, a logic '1' is detected.
After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by VHY to be detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.
Highlighted numbers are NOT in compliance with the published iButton standards. See comparison table below.
Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is
90% of VPUP and the time at which the voltage is 10% of VPUP.
e represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH.
d represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold of the bus
master.
To conserve battery power, use 8-bit temperature logging whenever possible.
This number was derived from a test conducted by Cemagref in Antony, France, in July of 2000.
http://www.cemagref.fr/English/index.htm Test Report No. E42.
Includes +0.1/-0.2oC calibration chamber measurement uncertainty.
Assumes using calibration memory with calibration equations for error compensation. Includes +0.1/-0.2oC calibration chamber
measurement uncertainty. Guaranteed by design.
STANDARD VALUES
DS1922L/T VALUES
PARAMETER
STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED
NAME
tSLOT (incl. tREC)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
61µs
(undef.)
7µs
(undef.)
65µs1)
(undef.)
9.5µs
(undef.)
tRSTL
480µs
(undef.)
48µs
80µs
690µs
720µs
70µs
80µs
tPDH
15µs
60µs
2µs
6µs
15µs
63.5µs
2µs
7µs
tPDL
60µs
240µs
8µs
24µs
60µs
287µs
7µs
28µs
tW0L
60µs
120µs
6µs
16µs
60µs
120µs
1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.
7.5µs
12µs
PHYSICAL SPECIFICATION
Size
Weight
Safety
See mechanical drawing
Ca. 3.3 grams
Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus,
approval under Entity Concept for use in Class I,
Division 1, Group A, B, C, and D Locations (application
pending)
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