DS1843 Ver la hoja de datos (PDF) - Maxim Integrated

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Fabricante

DS1843

Fast Sample-and-Hold Circuit

Maxim Integrated 

Fast Sample-and-Hold Circuit

CURRENT

MIRROR OUTPUT

CPAR

RIN

DS1843

INPUT MODEL

VINP

RSW

CIN

CS

VINN

CIN

RSW

CS

Figure 1. Input Impedances for Settling Time Calculations Diagram

Applications Information

Power-Supply Decoupling

To achieve the best results when using the DS1843,

decouple the power-supply pin, VCC, with a 0.01µF or

0.1µF capacitor. Use a high-quality X7R or equivalent

ceramic surface-mount capacitor.

DS1843 Estimated Settling Time

The settling time is dependent on the gain ratio of the

current mirror used at the input of the DS1843. For

example, the MAX4007 includes a 10:1 ratio current

mirror. This requires a 5kΩ resistor to create a 1V full-

scale output with 2mA current input to the MAX4007.

This resistor can be decreased to 2.5kΩ by using the

DS1842, which has a 5:1 ratio current mirror.

Variable Definitions:

RIN: Input resistor. The current mirror creates a voltage

across this resistor.

RSW: Resistance of series switch that connects internal

circuitry to input pins after tIST time.

CIN: 7pF parasitic (ESD) capacitor.

CPAR: External parasitic capacitance. A current mirror's

output and typical trace capacitance are less than

10pF.

CS: 5pF sample capacitor.

tIST: Internal settling time based on tS from the AC elec-

trical specification. The minimum tS includes one time

constant. tIST removes this time constant.

tRC: RC settling time of the input.

Figure 1 shows the simplified diagram of input imped-

ances for settling time calculations. Sample time is

divided into two parts:

1) tIST: Internal settling time (max 250ns). During this

time, voltage VIN (VINP - VINN) rises with a time con-

stant of:

RIN x (CIN + CPAR)

2) tRC: During this period two things happen:

a. Input VIN keeps increasing from its value at tIST

to its final value with a new time constant of:

( ) ( ) ( ) ⎧

⎨

⎩

RIN

×

CIN + CPAR

2

+

RSW × CS

2⎫

⎬

⎭

b. RSW and CS track this VIN (input) with a time con-

stant of RSW x CS, which is 12.5ns (worst case).

Example:

Approximate accuracy calculations can be done for an

input voltage based on the above impedance values.

These calculations can be divided into three parts.

1) Accuracy of input at tIST (250ns):

−t1

Accuracy = 1− e ( ⎡⎣RIN × CIN +CPAR )⎤⎦

where t1 = tIST = 250ns.

At tIST the internal circuit tags input impedance.

This causes charge redistribution to occur, which

causes a dip in the input voltage. The worst-case

value of the input voltage at tIST is:

⎡

−tIST

⎤

( ) ⎡

VIN@ tIST

= ⎢1−

⎣⎢

CS

CIN + CPAR + CS

⎤

⎥

⎦⎥

×

⎢

⎢1 −

⎢

⎣⎢

e

( ⎡⎣RIN × CIN +CPAR

)⎤⎦

⎥

⎥

⎥

⎦⎥

×

VIN

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