DS1843(2009) Ver la hoja de datos (PDF) - Maxim Integrated
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DS1843 Datasheet PDF : 8 Pages
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Fast Sample-and-Hold Circuit
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) (See the Timing Diagram.)
PARAMETER
Sample Time Minimum (Note 3)
Delay Time Minimum
Output Time
Hold Time
Output Step Recovery Time
(Note 6)
SYMBOL
tS
tDEL
tOUT
tHOLD
tREC
CONDITIONS
VOUT is within 1%
VOUT is within 35%
(Note 4)
Delay from SEN falling edge until valid
output at VOUT to 1% accuracy
(Note 5)
1V step, DEN = high
3V step, DEN = high or low
MIN
300
260
10
tOUT
TYP
MAX UNITS
ns
ns
2
μs
100
μs
2
μs
3.5
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note 2: Guaranteed by design.
Note 3: VOUT at the end of the 10μs hold time is within specified % of VIN during the sample window; a 2.5kΩ resistor connected in
series to both VINP and VINN (VINP - VINN = 1V). External capacitance to ground for both VINP and VINN is approximately 10pF.
Note 4: The sampling capacitor must be removed from the input signal before the input signal changes. Therefore, the SEN pin
must be low for a short period of time, tDEL, before the input changes.
Note 5: VOUT at the end of the hold time is within 1% of VIN during the sample window (VINP - VINN = 1V).
Note 6: Voltage step applied across VOUTP to VOUTN through a 5pF capacitor connected to each pin. This models the load presented
by an ADC while it is sampling the DS1843’s output. See the Output Buffer section. Settled within 1% of initial voltage.
Timing Diagram
VINP - VINN
SEN
tS
tDEL
VOUTP - VOUTN
tOUT
VOLTAGE INVALID
tHOLD
tREC
tADC:ST
tADC:CT
EXTERNAL
ADC DATA
tADC:ST = EXTERNAL ADC SAMPLING TIME.
tADC:CT = EXTERNAL ADC CONVERSION TIME.
DEN IS CONNECTED TO VCC FOR DIFFERENTIAL OUTPUT.
NOTE: THIS TIMING DIAGRAM IS APPLICABLE FOR SINGLE-ENDED AND DIFFERENTIAL OUTPUT CONFIGURATIONS.
DATA VALID
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