DS1073 Ver la hoja de datos (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS1073 Datasheet PDF : 18 Pages
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Figure 6
DS1073
tM = PERIOD OF MCLK
td = PROP DELAY FROM MCLK TO OUT
tOUTH = WIDTH OF OUTPUT PULSE
MAX VALUE OF tdis = tSUEM + td + tOUTH + tM
MIN VALUE OF tdis = tSUEM + td + tOUTH
SELECT TIMING
If the PDN bit is set to 0, the PDN / SELX pin can be used to switch between the internal oscillator and an
externalor crystal reference. The “Enabling Sequencer” is again employed to ensure this transition occurs
in a glitch-free fashion. Two asynchronous clock signals are involved, INTCLK is the internal reference
oscillator divided by one or whatever value of M is selected. EXTCLK is the clock signal fed into the
OSCIN pin, or the clock resulting from a crystal connected between OSCIN and XTAL. The behavior of
OUT0 is described in the following paragraphs, the OUT pin will behavior similarly but will be divided
by N.
FROM INTERNAL TO EXTERNAL CLOCK
This is accomplished by a high to low transition on the SELX pin. This transition is detected on the
falling edge of INTCLK. The output OUT0 will be held low for a minimum of half the period of
INTCLK (tI/2), then if EXTCLK is low it will be routed through to OUT0. If EXTCLK is high the
switching will not occur until EXTCLK returns to a low level.
Figure 7
Depending on the relative timing of the SELX signal and the internal clock, there may be up to one full
cycle of tI on the output after the falling edge of SELX . Then, the “low” time (tLOW) between output
pulses will be dependent on the relative timing between tI and tE. The time interval between the falling
edge of SELX and the first rising edge of the externally derived clock is tSIE. Approximate maximum and
minimum values of these parameters are:
tLOW (min) = tI/2
tLOW (max) = tI/2 + tE
tSIE (min) = tI/2
tSIE (max) = 3tI/2 + tE
NOTE:
In each case there will be a small additional delay due to internal propagation delays.
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