DM74S299 Ver la hoja de datos (PDF) - Fairchild Semiconductor

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DM74S299

3-STATE 8-Bit Universal Shift/Storage Register

Fairchild Semiconductor 

Function Table

Inputs

Inputs/Outputs

Outputs

Mode

Function

Output

Clear Select

Control

Clock Serial A/QA B/QB C/QC D/QD E/QE F/QF G/QG H/QH QA′ QH′

S1

S0

G1

G2

(Note 1) (Note 1)

SL SR

Clear L X L

L

L

X XX L L L L L L L L L L

L LX

L

L

X XX L L L L L L L L L L

Hold H L L

L

H XX

L

Shift H L H

L

Right

L

X X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0

L

L X X QA0 QB0 QC0 QD0 QE0 QF0 QG0 QH0 QA0 QH0

L

↑ X H H QAn QBn QCn QDn QEn QFn QGn H QGn

H LH

L

Shift H H L

L

Left

L

↑ X L L QAn QBn QCn QDn QEn QFn QGn L QGn

L

↑ H X QBn QCn QDn QEn QFn QGn QHn H QBn H

H HL

L

Load H H H X

L

↑ L X QBn QCn QDn QEn QFn QGn QHn L QBn L

X

↑ XX a b c d e f g h a h

a...h = The level of the steady-state input at inputs A through H, respectively. These data are loaded into the flip-flops while the flip-flop outputs are isolated

from the input/output terminals.

H = HIGH Level

L = LOW Logic Level

X = Either LOW or HIGH Logic Level

QA0...QH0 = The output logic level of QX before the indicated input conditions were established.

QAn...QHn = The output logic level before the active transition (↑) of the clock input.

Note 1: When one or both output controls are HIGH the eight input/output terminals are disabled to the high-impedance state; however, sequential operation

or clearing of the register is not affected

Logic Diagram

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