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PEEL22LV10AZ Ver la hoja de datos (PDF) - International Cmos Technology

Número de pieza
componentes Descripción
Fabricante
PEEL22LV10AZ
International-Cmos
International Cmos Technology International-Cmos
PEEL22LV10AZ Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
PEELTM 22LV10AZ
Table 6 - A.C. Electrical Characteristics
(Over the operating range9)
-25
I-35
Symbol
Parameter
3V±10% 3.3V±10% 3V±10% 3.3V±10% Units
tPD
tOE
tOD
tCO1
tCO2
tCF
tSC
tHC
tCL, tCH
tCP
fMAX1
fMAX2
fMAX3
tAW
tAP
tAR
tRESET
Input6 to non-registered output in continuous
mode13
Input6 to output enable7
Input6 to output disable7
Clock to output
Clock to comb. Output delay via internal
registered feedback
Clock to Feedback
Input6 or feedback setup to clock
Input6 hold after clock
Clock low time, clock high time9
Min clock period Ext (tSC + tCO1)
Internal feedback 1/ (tSC + tCF) 12
External Feedback (1/ tCP) 12
No Feedback 1/ (tCL + tCH) 12
Asynchronous Reset Pulse Width
Input to Asynchronous Reset
Asynchronous Reset recovery time
Power-on reset time for registers in clear state14
Min Max Min Max Min Max Min Max
30
25
40
35
30
25
40
35
30
25
40
35
20
15
28
25
40
35
56
49
14
9
20
13
20
15
28
21
0
0
0
0
20
13
28
18
40
30
56
39
29.4
41.6
20.8
29.4
25
33.3
17.9
25.6
25
38.4
17.9
27.7
30
25
40
35
30
25
40
35
30
25
40
35
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
µs
Inputs I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Figure 7 - Switching Waveforms
Notes:
1. Minimum DC input is -0.5V, however, inputs may undershoot to -
2.0V for periods less than 20 ns.
2. VI and VO are not specified for program/verify operation.
3. The Supply Voltage range of 2.7 to 3.6V was chosen to allow
this part to be used in both 3V 10% and 3.3V 10% applications.
4. Test Points for Clock and VCC in tR and tF are referenced at the
10% and 90% levels.
5. I/O pins are 0V and VCC.
6. "Input" refers to an input pin signal.
7. tOE is measured from input transition to VREF 0.1V, TOD is
measured from input transition to VOH -0.1V or VOL +0.1V; VREF
=VL
8. Capacitances are tested on a sample basis.
9. Test conditions assume: signal transition times of 3ns or less
from the 10% and 90% points, timing reference levels of 1.5V
(Unless otherwise specified).
10. Test one output at a time for duration of less than 1 second.
11. ICC for a typical application: This parameter is tested with the
device programmed as a 10-bit Counter.
12. Parameters are not 100% tested. Specifications are based on
initial characterization and are tested after any design process
modification that might affect operational frequency.
13. tPD, tOE, tOD, tCO, tSC, and tAP are approximately 5 ns, slower on the
first transaction from sleep mode.
14. All inputs at GND.
8
04-02-037D

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