NX29F010-35W Ver la hoja de datos (PDF) - NexFlash -> Winbond Electronics

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NX29F010-35W

1M-BIT (128K x 8-bit) CMOS, 5.0V Only ULTRA-FAST SECTORED FLASH MEMORY

NexFlash -> Winbond Electronics 

NX29F010

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system

also should note whether the value of DQ5 is high (see the

section on DQ5). If it is, the system should then determine

again whether the toggle bit is toggling, since the toggle bit

may have stopped toggling just as DQ5 went high. If the

toggle bit is no longer toggling, the device has successfully

completed the program or erase operation. If it is still

toggling, the device did not complete the operation suc-

cessfully, and the system must write the reset command to

return to reading array data.

The remaining scenario is that the system initially deter-

mines that the toggle bit is toggling and DQ5 has not gone

high. The system may continue to monitor the toggle bit and

DQ5 through successive read cycles, determining the

status as described in the previous paragraph. Alterna-

tively, it may choose to perform other system tasks. In this

case, the system must start at the beginning of the

algorithm when it returns to determine the status of the

operation (top of Figure 8).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a "1." This is a failure condition

that indicates the program or erase cycle as not success-

fully completed.

The DQ5 failure condition may appear if the system tries to

program a "1" to a location that is previously programmed

to "0." Only an erase operation can change a "0" back to a

"1." Under this condition, the device halts the operation, and

when the operation has exceeded the timing limits, DQ5

produces a "1."

Under both these conditions, the system must issue the

reset command to return the device to reading array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the sys-

tem may read DQ3 to determine whether or not an erase

operation has begun. (The sector erase timer does not apply

to the chip erase command.) If additional sectors are

selected for erasure, the entire time-out also applies after

each additional sector erase command. When the time-out

is complete, DQ3 switches from "0" to "1." The system may

ignore DQ3 if the system can guarantee that the time

between additional sector erase commands will always be

less than 50 µs. See also the "Sector Erase Command

Sequence" section.

After the sector erase command sequence is written, the

system should read the status on DQ7 (Data Polling) or

DQ6 (Toggle Bit I) to ensure the device has accepted the

command sequence, and then read DQ3. If DQ3 is "1", the

internally controlled erase cycle has begun; all further

commands are ignored until the erase operation is com-

plete. If DQ3 is "0", the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status of

DQ3 prior to and following each subsequent sector erase

command. If DQ3 is high on the second status check, the

last command might not have been accepted. Table 6

shows the outputs for DQ3.

Table 6. Write Operation Status

Operation

DQ7(1) DQ6 DQ5(2) DQ3

Embedded

DQ7# Toggle 0 N/A

Program Algorithm

Embedded

Erase Algorithm

0 Toggle 0

1

Notes:

1. DQ7 requires a valid address when reading status

information.

2. DQ5 switches to '1' when an Embedded Program or

Embedded Erase operation has exceeded the maximum

timing limits. See "DQ5: Exceeded Timing Limits" for more

information.

12

NexFlash Technologies, Inc.

NXPF001F-0600

06/22/00 ©

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