TQ8034 Ver la hoja de datos (PDF) - TriQuint Semiconductor
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TQ8034 Datasheet PDF : 16 Pages
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TQ8034
PRELIMINARY DATA SHEET
Circuit Description
Data inputs
The 34 input channels are differential LVPECL
compatible with on-chip 50-Ohm termination to VTT.
Unused input-pairs should have one side connected to
GND through a 500-Ohm or smaller resistor to prevent
unwanted oscillations. See figure 6 for examples of DC
and AC coupled termination.
Configuration Modes
There are two primary modes for configuring the
TQ8034; Sequential and Multicast. Sequential mode is
used to program one input to one output per LOAD
cycle and Multicast is used to program one input to
multiple outputs per LOAD cycle. Both modes allow
either a user defined input port assignment or an
internal default input port assignment.
Data outputs
The 34 output channels are differential LVPECL
compatible and designed to be terminated through 50-
Ohms to VDD-2.0V. Unused outputs can be left un-
terminated to save power. See figure 6 for examples of
DC and AC coupled termination.
Control Inputs
The control inputs are TTL compatible. Unconnected
inputs will default to logic HI levels.
Configuration Storage
Each of the 34 output channels has two sets of
configuration storage registers. The registers are built
using transparent latches which are controlled by the
LOAD and CONFIGURE inputs. The first set of latches,
or program register, stores a new input configuration
prior to application to the switch core. The second set
of latches, or configuration register, stores the
configuration that is applied to the switch core. The
use of two sets of program storage latches allows new
configurations to be loaded without disturbing the
existing configuration. The two-stage architecture also
allows all of the new configurations to be applied to the
switch core simultaneously.
The default input port assignment for each output port
is the output's corresponding input port (IN0 to OUT0,
IN1 to OUT1, etc.). This default configuration is
referred to as pass-through.
All programming modes result in the loading of a new
configuration into the appropriate output port
PROGRAM (first stage) registers. Changing the
contents of the PROGRAM registers does not change
the configuration of the switch core. The configuration
of the switch core is updated following the assertion of
CONFIGURE. CONFIGURE is a global input that
simultaneously transfers the contents of all PROGRAM
registers into their second stage CONFIGURATION
registers. The data is latched into the CONFIGURATION
register when CONFIGURE is de-asserted.
The integrity of the data flowing through the switch
core is maintained during the load cycle. The integrity
of the data flowing through the switch core to outputs
that do not receive a new configuration is also
maintained during the configure cycle. Data integrity is
unknown on output ports receiving a new input port
configuration for a time Tdcf after assertion of
CONFIGURE (see timing diagrams).
The CONFIGURE inputs can be tied to a "HI" level or
asserted simultaneously with LOAD. In this case, the
new configuration will be applied to the switch
multiplexer when LOAD is asserted.
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