NT7501 Ver la hoja de datos (PDF) - Novatek Microelectronics
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NT7501 Datasheet PDF : 38 Pages
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NT7501
CS1
CS2
SI
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1
SCL
12345
6
78
9 10 11 12 13 14
A0
Chip Select Inputs
Figure 1.
The NT7501 has two chip select pads, CS1 and CS2 can interface to a microprocessor when CS1 is low and CS2 is high.
When these pads are set to any other combination, D0 to D7 are high impedance and A0, E and R W inputs are disabled.
When the serial input interface is selected. the shift register and counter are reset.
Access to Display Data RAM and Internal Registers
The NT7501 can perform a series of pipeline processes between the LSI’s using the bus holder of the internal data bus in order
to match the operating frequency of the display RAM and the internal registers with that of the microprocessor. For example, the
microprocessor reads data from the display RAM in the first read (dummy) cycle, stores it in the bus holder and outputs it onto
the system bus in the next data read cycle.
Also, the microprocessor temporarily stores display data in the bus holder, and stores it in the display RAM until the next data
write cycle starts.
When viewed from the microprocessor, the NT7501 access speed greatly depends on the cycle time rather than the access
time to the display RAM (tACC). It shows the data transfer speed to/from the microprocessor can increase. If the cycle time is
inappropriate, the microprocessor can insert the NOP instruction that is equivalent to the wait cycle setup. However, there is a
restriction in the display RAM read sequence. When an address is set, the specified address data is NOT output at the read
instruction immediately following. Instead, the address data is output only during second data read. A single dummy read must
be inserted after the address setup and after write cycle (refer to Figure2).
MPU
A0
E
R/W
DATA
Address preset
Read signal
Internal
timing
Column address
N
N
n
Preset
N
Incremented
N+1
n+1
N+2
BUS holder
N
Set address n Dummy read
n
n+1
n+2
Data Read address n Data Read address n+1
Figure 2.
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