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DAC8043FZ

12-Bit Serial Input Multiplying CMOS D/A Converter

Analog Devices 

DAC8043

PARAMETER DEFINITIONS

INTEGRAL NONLINEARITY (INL)

This is the single most important DAC specification. ADI mea-

sures INL as the maximum deviation of the analog output (from

the ideal) from a straight line drawn between the end points. It

is expressed as a percent of full-scale range or in terms of LSBs.

Refer to PMI 1988 Data Book section 11 for additional digital-

to-analog converter definitions.

INTERFACE LOGIC INFORMATION

The DAC8043 has been designed for ease of operation. The

timing diagram illustrates the input register loading sequence.

Note that the most significant bit (MSB) is loaded first.

Once the input register is full, the data is transferred to the

DAC register by taking LD momentarily low.

DIGITAL SECTION

The DAC8043’s digital inputs, SRI, LD, and CLK, are TTL

compatible. The input voltage levels affect the amount of cur-

rent drawn from the supply; peak supply current occurs as the

digital input (VIN) passes through the transition region. See the

Supply Current vs. Logic Input Voltage graph located under the

typical performance characteristics curves. Maintaining the digi-

tal input voltage levels as close as possible to the supplies, VDD

and GND, minimizes supply current consumption.

The DAC8043’s digital inputs have been designed with ESD re-

sistance incorporated through careful layout and the inclusion of

input protection circuitry. Figure 1 shows the input protection

diodes and series resistor; this input structure is duplicated on

each digital input. High voltage static charges applied to the in-

puts are shunted to the supply and ground rails through forward

biased diodes. These protection diodes were designed to clamp

the inputs to well below dangerous levels during static discharge

conditions.

GENERAL CIRCUIT INFORMATION

The DAC8043 is a 12-bit multiplying D/A converter with a very

low temperature coefficient. It contains an R-2R resistor ladder

network, data input and control logic, and two data registers.

Figure 1. Digital Input Protection

The digital circuitry forms an interface in which serial data can

be loaded under microprocessor control into a 12-bit shift regis-

ter and then transferred, in parallel, to the 12-bit DAC register.

A simplified circuit of the DAC8043 is shown in Figure 2. An

inverted R-2R ladder network consisting of silicon-chrome,

highly-stable (+50 ppm/°C) thin-film resistors, and twelve pairs

of NMOS current-steering switches.

These switches steer binarily weighted currents into either IOUT

or GND; this yields a constant current in each ladder leg, regard-

less of digital input code. This constant current results in a con-

stant input resistance at VREF equal to R. The VREF input may

be driven by any reference voltage or current, ac or dc that is

within the limits stated in the Absolute Maximum Ratings.

The twelve output current-steering NMOS FET switches are in

series with each R-2R resistor, they can introduce bit errors if all

are of the same RON resistance value. They were designed such

that the switch “ON” resistance be binarily scaled so that the

voltage drop across each switch remains constant. If, for ex-

ample, switch 1 of Figure 2 was designed with an “ON” resis-

tance of 10 Ω, switch 2 for 20 Ω, etc., a constant 5 mV drop will

then be maintained across each switch.

Write Cycle Timing Diagram

–6–

REV. C

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