CYRF69213(2007) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CYRF69213 Datasheet PDF : 85 Pages
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CYRF69213
function, which operates at higher supply voltage. The internal
SPIO pins between the MCU function and radio function
should be connected with a regulated voltage of 3.3V (by
setting [bit4] of Registers P13CR, P14CR, P15CR, and
P16CR of the MCU function) and the internal 3.3V regulator of
the MCU function should be turned on.
SPI Connects to External Devices
The three SPI wires, MOSI, SCK, and SS are also drawn out
of the package as external pins to allow the user to interface
their own external devices (such as optical sensors and
others) through SPI. The radio function also has its own SPI
wires MISO and IRQ, which can be used to send data back to
the MCU function or send an interrupt request to the MCU
function. They can also be configured as GPIO pins.
Bit#
Bit Name
7
6
DIR
INC
Figure 6. SPI Transaction Format
Byte 1
[5:0]
Address
Byte 1+N
[7:0]
Data
CPU Architecture
This family of microcontrollers is based on a high-perfor-
mance, 8-bit, Harvard-architecture microprocessor. Five
registers control the primary operation of the CPU core. These
registers are affected by various instructions, but are not
directly accessible through the register space by the user.
Table 2. CPU Registers and Register Names
Register
Flags
Program Counter
Accumulator
Stack Pointer
Register Name
CPU_F
CPU_PC
CPU_A
CPU_SP
Index
CPU_X
The 16-bit Program Counter Register (CPU_PC) allows for
direct addressing of the full eight Kbytes of program memory
space.
The Accumulator Register (CPU_A) is the general-purpose
register that holds the results of instructions that specify any
of the source addressing modes.
The Index Register (CPU_X) holds an offset value that is used
in the indexed addressing modes. Typically, this is used to
address a block of data within the data memory space.
The Stack Pointer Register (CPU_SP) holds the address of the
current top-of-stack in the data memory space. It is affected by
the PUSH, POP, LCALL, CALL, RETI, and RET instructions,
which manage the software stack. It can also be affected by
the SWAP and ADD instructions.
The Flag Register (CPU_F) has three status bits: Zero Flag bit
[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global
Interrupt Enable bit [0] is used to globally enable or disable
interrupts. The user cannot manipulate the Supervisory State
status bit [3]. The flags are affected by arithmetic, logic, and
shift operations. The manner in which each flag is changed is
dependent upon the instruction being executed (for example,
AND, OR, XOR). See Table 19.
CPU Registers
Flags Register
The Flags Register can only be set or reset with logical instruction.
Table 3. CPU Flags Register (CPU_F) [R/W]
Bit #
7
6
5
Field
Reserved
Read/Write
–
–
–
Default
0
0
0
4
3
2
1
0
XIO
Super
Carry
Zero
Global IE
R/W
R
RW
RW
RW
0
0
0
1
0
Document #: 001-07552 Rev. *B
Page 9 of 85
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