CYRF69103(2007) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CYRF69103
(Rev.:2007)

Programmable Radio on Chip Low Power

Cypress Semiconductor 

CYRF69103

Data Transmission Modes and Data Rates

The SoC supports four different data transmission modes:

• In GFSK mode, data is transmitted at 1 Mbps, without any

DSSS.

• In 8DR mode, 8 bits are encoded in each

DATA_CODE_ADR derived code symbol transmitted.

• In DDR mode, 2-bits are encoded in each

DATA_CODE_ADR derived code symbol transmitted. (As

in the CYWUSB6934 DDR mode).

• In SDR mode, 1 bit is encoded in each DATA_CODE_ADR

derived code symbol transmitted. (As in the CYWUSB6934

standard modes.)

Both 64-chip and 32-chip DATA_CODE_ADR codes are

supported. The four data transmission modes apply to the data

after the SOP. In particular the length, data, and CRC16 are all

sent in the same mode. In general, lower data rates reduces

packet error rate in any given environment.

The CYRF69103 IC supports the following data rates:

• 1000-kbps (GFSK)

• 250-kbps (32-chip 8DR)

• 125-kbps (64-chip 8DR)

• 62.5-kbps (32-chip DDR)

• 31.25-kbps (64-chip DDR)

• 15.625-kbps (64-chip SDR)

Lower data rates typically provide longer range and/or a more

robust link.

Link Layer Modes

The CYRF69103 IC device supports the following data packet

framing features:

SOP – Packets begin with a 2-symbol Start of Packet (SOP)

marker. This is required in GFSK and 8DR modes, but is

optional in DDR mode and is not supported in SDR mode; if

framing is disabled then an SOP event is inferred whenever

two successive correlations are detected. The

SOP_CODE_ADR code used for the SOP is different from that

used for the “body” of the packet, and if desired may be a

different length. SOP must be configured to be the same

length on both sides of the link.

EOP – There are two options for detecting the end of a packet.

If SOP is enabled, then a packet length field may be enabled.

GFSK and 8DR must enable the length field. This is the first

8 bits after the SOP symbol, and is transmitted at the payload

data rate. If the length field is enabled, an End of Packet (EOP)

condition is inferred after reception of the number of bytes

defined in the length field, plus two bytes for the CRC16 (if

enabled—see below). The alternative to using the length field

is to infer an EOP condition from a configurable number of

successive non-correlations; this option is not available in

GFSK mode and is only recommended when using SDR

mode.

CRC16 – The device may be configured to append a 16-bit

CRC16 to each packet. The CRC16 uses the USB CRC

polynomial with the added programmability of the seed. If

enabled, the receiver will verify the calculated CRC16 for the

payload data against the received value in the CRC16 field.

The starting value for the CRC16 calculation is configurable,

and the CRC16 transmitted may be calculated using either the

loaded seed value or a zero seed; the received data CRC16

will be checked against both the configured and zero CRC16

seeds.

CRC16 detects the following errors:

• Any one bit in error

• Any two bits in error (no matter how far apart, which column,

and so on)

• Any odd number of bits in error (no matter where they are)

• An error burst as wide as the checksum itself

Figure 2 shows an example packet with SOP, CRC16 and

lengths fields enabled.

Figure 2. Example Default Packet Format

Preamble

n x 16us

2nd Framing

Symbol*

P

SOP 1

SOP 2

1st Framing

Symbol*

Length

Packet

length

1 Byte

Period

Payload Data

CRC 16

*Note:32 or 64us

Packet Buffers and Radio Configuration Registers

Packet data and configuration registers are accessed through

the SPI interface. All configuration registers are directly

addressed through the address field in the SPI packet (as in

the CYWUSB6934). Configuration registers are provided to

allow configuration of DSSS PN codes, data rate, operating

mode, interrupt masks, interrupt status, and others.

Packet Buffers

All data transmission and reception uses the 16-byte packet

buffers—one for transmission and one for reception.

The transmit buffer allows a complete packet of up to 16 bytes

of payload data to be loaded in one burst SPI transaction, and

then transmitted with no further MCU intervention. Similarly,

the receive buffer allows an entire packet of payload data up

to 16 bytes to be received with no firmware intervention

required until packet reception is complete.

Document #: 001-07611 Rev *B

Page 5 of 73

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