CYRF69103(2007) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CYRF69103 Datasheet PDF : 73 Pages
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CYRF69103
Pinout
Pin
41
Name
E-pad
Pinout Diagram
GND
Function/Description
Figure 1. Pinout
40-pin Lead-Free QFN 6x6 mm LY40
Corner
tabs
P0.4 1
XTAL 2
VCC 3
P0.3 4
P0.1 5
VBAT 6
VCC 7
P2.1 8
VBAT 9
RFBIAS 10
CYRF69103
WirelessUSB LP
* E-PAD Bottom Side
30 XOUT / GPIO
29 MISO / GPIO
28 P1.5 / MOSI
27 IRQ / GPIO
26 P1.4 / SCK
25 P1.3 / SS
24 P1.2 / VREG
23 VDD_Micro
22 P1.1
21 P1.0
Functional Block Overview
All the blocks that make up the PRoC LP are presented here.
2.4-GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel-matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to +4 dBm transmit power, with an output power
control range of 34 dB in 7 steps. The supply current of the
device is reduced as the RF output power is reduced.
Table 1. Internal PA Output Power Step Table
PA Setting
Typical Output Power (dBm)
7
+4
6
0
5
–5
4
–10
3
–15
Table 1. Internal PA Output Power Step Table
PA Setting
Typical Output Power (dBm)
2
–20
1
–25
0
–30
Frequency Synthesizer
Before transmission or reception may commence, it is
necessary for the frequency synthesizer to settle. The settling
time varies depending on channel; 25 fast channels are
provided with a maximum settling time of 100 µs.
The “fast channels” (<100-µs settling time) are every 3rd
frequency, starting at 2400 MHz up to and including 2472 MHz
(i.e., 0,3,6,9…….69 & 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception and CRC16
generation and checking, as well as EOP detection and length
field.
Document #: 001-07611 Rev *B
Page 4 of 73
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