CYM1464-25 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CYM1464-25 Datasheet PDF : 8 Pages
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CYM1464
Switching Characteristics Over the Operating Range[3]
1464-20
1464-22
1464-25
1464-30
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
20
22
25
30
ns
tAA
Address to Data Valid
20
22
25
30
ns
tOHA
Data Hold from Address Change 5
5
5
5
ns
tACS
CS LOW to Data Valid
20
22
25
30
ns
tDOE
OE LOW to Data Valid
13
13
15
15
ns
tLZOE
OE LOW to Low Z
0
0
0
0
ns
tHZOE
OE HIGH to High Z
0
10
0
10
0
10
0
10
ns
tLZCS
CS LOW to Low Z
tHZCS
CS HIGH to High Z[4]
WRITE CYCLE[5]
5
5
5
10
ns
0
15
0
15
0
15
0
20
ns
tWC
tSCS
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Write Cycle Time
CS LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z[4]
20
22
25
30
ns
15
17
20
25
ns
15
15
20
25
ns
3
3
3
3
ns
5
5
5
5
ns
15
15
15
20
ns
12
12
15
15
ns
2
2
2
2
ns
0
0
0
0
ns
15
15
15
15
ns
Switching Characteristics Over the Operating Range [3]
1464-35
1464-45
1464-55
Parameter
Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
35
45
55
ns
tAA
Address to Data Valid
35
45
55
ns
tOHA
Data Hold from Address Change
5
5
5
ns
tACS
CS LOW to Data Valid
35
45
55
ns
tDOE
OE LOW to Data Valid
20
25
30
ns
tLZOE
OE LOW to Low Z
0
0
0
ns
tHZOE
OE HIGH to High Z
0
15
0
15
0
15
ns
tLZCS
tHZCS
CS LOW to Low Z
CS HIGH to High Z[4]
10
10
10
ns
0
20
0
20
0
20
ns
Notes:
3. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
4. tHZCS and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
5. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05272 Rev. **
Page 3 of 8
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