CY8C20767-24FDXC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY8C20767-24FDXC
Cypress Semiconductor
CY8C20767-24FDXC Datasheet PDF : 43 Pages
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CY8C20xx7/S
16-pin QFN (10 Sensing Inputs)[7]
Table 2. Pin Definitions – CY8C20237, CY8C20247/S [8]
Pin
No.
Type
Name
Digital Analog
Description
1 I/O
I
P2[5] Crystal output (XOut)
2 I/O
3 IOHR
4 IOHR
I
P2[3] Crystal input (XIn)
I
P1[7] I2C SCL, SPI SS
I
P1[5] I2C SDA, SPI MISO
5 IOHR
6 IOHR
I
P1[3] SPI CLK
I
P1[1] ISSP CLK[9], I2C SCL, SPI
MOSI
7
Power
8 IOHR
I
VSS Ground connection
P1[0] ISSP DATA[9], I2C SDA, SPI
CLK[10]
9 IOHR
I
P1[2] Driven Shield Output (optional)
10 IOHR
I
P1[4] Optional external clock
(EXTCLK)
11
Input
XRES Active high external reset with
internal pull-down
12 IOH
I
P0[4]
13
Power
14 IOH
I
VDD Supply voltage
P0[7]
15 IOH
I
P0[3] Integrating input
16 IOH
I
P0[1] Integrating input
Figure 3. CY8C20237, CY8C20247/S Device
AI , XOut, P2[5]
AI , XIn, P2[3]
AI , I2 C SCL, SPI SS, P1[7]
AI , I2 C SDA, SPI MISO, P1[5]
1
12
2 QFN 11
3 (Top View)10
4
9
P0[4] , AI
XRES
P1[4] , EXTCLK, AI
P1[2] , AI
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
7. No center pad.
8. 13 GPIOs = 10 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.
9. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives
resistive
resistive
low
low
for
for
512 sleep clock cycles and both the pins transition to
8 sleep clock cycles and transition to high impedance
high impedance state. On reset, after XRES de-asserts,
state. Hence, during power-up or reset event, P1[1] and
the SDA and the SCL
P1[0] may disturb the
lIi2nCesbdusri.vUe se
alternate pins if you encounter issues.
10. Alternate SPI clock.
Document Number: 001-69257 Rev. *I
Page 8 of 43
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