CY8C20767-24FDXCT Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY8C20767-24FDXCT

1.8 V CapSense® Controller with SmartSense™ Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors

Cypress Semiconductor 

CY8C20xx7/S

30-ball WLCSP (24 Sensing Inputs)

Table 4. Pin Definitions – CY8C20767, CY8C20747 30-ball Part Pinout (WLCSP) [15]

Pin No.

Type

Digital Analog

Name

Description

A1

IOH

I

P0[2]

Driven Shield Output (optional)

A2

IOH

I

P0[6]

A3

Power

VDD

Supply voltage

A4

IOH

I

P0[1]

Integrating Input

A5

I/O

I

P2[7]

B1

I/O

I

P4[2]

B2

IOH

I

P0[0]

Driven Shield Output (optional)

B3

IOH

I

P0[4]

B4

IOH

I

P0[3]

Integrating Input

B5

I/O

I

P2[5]

Crystal Output (Xout)

C1

I/O

I

P2[2]

Driven Shield Output (optional)

C2

I/O

I

P2[4]

Driven Shield Output (optional)

C3

I/O

I

P0[7]

C4

IOH

I

P3[2]

C5

I/O

I

P2[3]

Crystal Input (Xin)

D1

I/O

I

P2[0]

D2

I/O

I

P3[0]

D3

I/O

I

P3[1]

D4

I/O

I

P3[3]

D5

I/O

I

P2[1]

E1

Input

XRES Active high external reset with

internal pull-down

E2

IOHR

I

P1[6]

E3

IOHR

I

P1[4]

Optional external clock input

(EXT CLK)

E4

IOHR

I

P1[7]

I2C SCL, SPI SS

E5

IOHR

I

P1[5]

I2C SDA, SPI MISO

F1

IOHR

I

P1[2]

Driven Shield Output (optional)

F2

IOHR

I

P1[0]

ISSP DATA[16], I2C SDA, SPI

CLK[17]

F3

Power

VSS

Supply ground

F4

IOHR

I

P1[1]

ISSP CLK[16], I2C SCL, SPI

MOSI

F5

IOHR

I

P1[3]

SPI CLK

LEGEND: A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output

Figure 5. CY8C20767, CY8C20747 30-ball

WLCSP

Bottom View

54

3

2

1

A

B

C

D

E

F

Top View

12 3 4 5

A

B

C

D

E

F

Notes

15. 27 GPIOs = 24 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.

16. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives

resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive

resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use

alternate pins if you encounter issues.

17. Alternate SPI clock.

Document Number: 001-69257 Rev. *I

Page 10 of 43

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