CY7C955 Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
CY7C955 Datasheet PDF : 78 Pages
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PRELIMINARY
CY7C955
Receive Power
Name
Pin No
RAVD1
30
I/O
Power
RAVD2
36
Power
RAVD3
24
Power
RAVD4
32
Power
Core Power
Name
VDDI
VDDO
Pin No
20, 61,
107
55, 73,
81, 114
I/O
Power
Power
Ground
Name
TAVS1
TAVS2
TAVS3
TXVSS
Pin No I/O
5
Ground
7
Ground
11
Ground
17
Ground
RAVS1
RAVS2
RAVS3
RAVS4
RVSSO
VSSI
VSSO
VSS
ATP1,
ATP2,
ATP3
31
Ground
37
Ground
29
Ground
35
Ground
21
19, 62,
106,48
56, 72,
80, 113,
49
1, 38,
39, 46,
47, 64,
65, 102,
103,
128
40, 3,
46
Ground
Ground
Ground
Ground
I/O
Description
The power pin for receive clock and data recovery block reference circuitry. RAVD1 should
be connected to analog +5V.
The power pin for receive clock and data recovery block active loop filter and oscillator.
RAVD2 should be connected to analog +5V.
The power pin for the RXD± and ALOS± PECL inputs. RAVD3 should be connected to
analog +5V.
The power pin for the RRCLK± PECL inputs. RAVD4 should be connected to analog +5V.
Description
The core power pins should be connected to a well decoupled +5V DC in common with
VDDO.
The pad ring power pins should be connected to a well decoupled +5V DC in common
with VDDI.
Description
The ground pin for the transmit clock synthesizer reference circuitry. TAVS1 should be
connected to analog GND.
The ground pin for the transmit clock synthesizer oscillator. TAVS2 should be connected
to analog GND.
The ground pin for the transmit PECL inputs. TAVS3 should be connected to analog GND.
The transmit pad ground is the return path for the TXC± and TXD± outputs. TXVSS is
physically isolated from the other device ground pins and should be noise-free for good
performance when driving category 5 unshielded twisted pair cabling.
The ground pin for receive clock and data recovery block reference circuitry. RAVS1 should
be connected to analog GND.
The ground pin for receive clock and data recovery block active loop filter and oscillator.
RAVS2 should be connected to analog GND.
The ground pin for the RRCLK± PECL inputs. RAVS3 should be connected to analog GND.
The ground pin for the RSD± and ALOS± PECL inputs. RAVS4 should be connected to
analog GND.
This pin is grounded for TXC± and RXDO±.
The core ground (VSSI) pins should be connected to GND in common with VSSO.
The pad ring ground (VSSO) pins should be connected to GND in common with VSSI.
These pins must be connected to GND for correct operation.
These Analog Test Points (ATPx) are for factory testing use only. These pins have to be
tied to GND for correct chip operation.
6
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