CY7C955 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C955 Datasheet PDF : 78 Pages
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PRELIMINARY
TABLE OF CONTENTS (continued)
Switching Waveforms
Functional Timing Diagram
Interface Termination and Biasing Schemes
Filter Pin Configuration
Ordering Information
Package Diagram
CY7C955
63
69
73
75
76
77
D[7:0]
A[7:0]
ALE
RDB
WRB
CSB
INTB
RSTB
RALM
Transmit
UTOPIA I/F
Transmit FIFO
4 Cell by 8 bit
Controller
Interface
Receive
UTOPIA I/F
Receive FIFO
4 Cell by 8 bit
Transmit
ATM Cell
Processor
Transmit
Path
Overhead
Processor
Configuration and Status
Register File
Error Monitoring
Receive
ATM Cell
Processor
Receive
Path
Overhead
Processor
Transmit
Line
Overhead
Processor
Receive
Line
Overhead
Processor
Transmit
Section
Overhead
Processor
Rate
Selection
Transmit
Clock
Multiplier &
Transmit
Buffer
Receive
Section
Overhead
Processor
SONET/SDH
Clock
Recovery
TXD±
TXC±
TRCLK±
ALOS±
RRCLK±
RXD±
RXDO±
7C955−1
Pin Descriptions
CY7C955 ATM-SONET/SDH Transceiver
Transmit Utopia Interface
Name
Pin
I/O
TDAT[7:0] 87−94 Input
TPRTY
95
Input
TSOC
96
Input
TFCLK
84
TWRENB 85
Input
Input
Description
Transmit Utopia data: Byte-wide data driven from the ATM to PHY layer. TDAT[7] is the
MSB.
Transmit Utopia Data Parity: Data parity calculated over TDAT[7:0]. Odd parity is as-
sumed unless the TXPTYP bit (Reg–63, bit 7) is set to even parity
Transmit Utopia Start of Cell: Assert TSOC HIGH when TDAT[7:0] contains the first
byte of an ATM cell. If TSOC is asserted sooner than 53 writes after the previous SOC,
an error condition will be generated. This input is optional after the first TSOC pulse.
Transmit Utopia Clock: Data transfer clock. Data is transferred to the AX on the rising
edge of TFCLK when TWRENB is asserted (LOW).
Transmit Utopia Data Enable: Enables the TFCLK input for data transfer to the AX. This
signal is active LOW.
2
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