CY7C68000 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C68000 Datasheet PDF : 14 Pages
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9.2.2
HS/FS Interface Timing–30 MHz
CLK
Control_In
TCSU_MIN
TCH_MIN
DataIn
Control_Out
DataOut
TDSU_MIN
TDH_MIN
TVSU_MIN
TVH_MIN
TCDO
TCCO
TCVO
Figure 9-2. 30-MHz Timing Interface Timing Constraints
CY7C68000
Table 9-2. 30 MHz Timing Interface Timing Constraints Parameters
Parameter
Description
Min.
Typ.
Max.
Unit
TCSU_MIN
TCH_MIN
TDSU_MIN
TDH_MIN
TCCO
Minimum set-up time for TXValid
20
Minimum hold time for TXValid
1
Minimum set-up time for Data (Transmit direction)
20
Minimum hold time for Data (Transmit direction)
1
Clock to Control Out time for TXReady, RXValid,
1
RXActive and RXError
ns
ns
ns
ns
20
ns
TCDO
TVSU_MIN
TVH_MIN
TCVO
Clock to Data out time (Receive direction)
1
Minimum set-up time for ValidH (transmit Direction)
20
Minimum hold time for ValidH (Transmit direction)
1
Clock to ValidH out time (Receive direction)
1
20
ns
ns
ns
20
ns
Notes
Document #: 38-08016 Rev. *H
Page 10 of 14
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