CY7C4282-15 Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY7C4282-15

64K/128K x 9 Deep Sync FIFOs with Retransmit and Depth Expansion

Cypress Semiconductor 

Switching Waveforms (continued)

Reset Timing [16]

tRSS

[17]

LD

tRS

RS

tRSR

REN, WEN

tRSF

EF,PAE

FF,PAF

tRSF

tRSF

Q0 – Q8

First Data Word Latency after Reset with Simultaneous Read and Write

CY7C4282

CY7C4292

[18]

OE=1

OE=0

WCLK

tDS

D0 –D8

D0 (FIRSTVALID WRITE)

D1

D2

WEN

tENS

RCLK

[19]

tFRL

tSKEW1

tREF

EF

D3

D4

REN

Q0 –Q8

OE

tOLZ

tA

tOE

[20]

tA

D0

D1

Note:

4282–9

16. The clocks (RCLK, WCLK) can be free-running during reset.

17. For standalone or width expansion configuration only.

18. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.

19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.

The Latency Timing applies only at the Empty Boundary (EF = LOW).

20. The first word is available the cycle after EF goes HIGH, always.

Document #: 38-06009 Rev. *B

Page 11 of 16

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