7C408A-15 Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
7C408A-15 Datasheet PDF : 16 Pages
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CY7C408A
CY7C409A
HF/AFE
COMPOSITE
INPUT READY
IR
SO
SI
OR
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
DI4
DO4
DI5
DO5
DI6
DO6
DI7
DO7
DI8 MR DO8
192 x 27 Configuration
IR
SO
SI
OR
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
DI4
DO4
DI5
DO5
DI6
DO6
DI7
DO7
DI8 MR DO8
IR
SO
SI
OR
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
DI4
DO4
DI5
DO5
DI6
DO6
DI7
DO7
DI8 MR DO8
IR
SO
SI
OR
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
DI4
DO4
DI5
DO5
DI6
DO6
DI7
DO7
DI8 MR DO8
IR
SO
SI
OR
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
DI4
DO4
DI5
DO5
DI6
DO6
DI7
DO7
DI8 MR DO8
IR
SO
SI
OR
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
DI4
DO4
DI5
DO5
DI6
DO6
DI7
DO7
DI8 MR DO8
HF/AFE
SHIFT OUT
COMPOSITE
OUTPUT READY
SHIFT IN
IR
SO
IR
SO
IR
SO
SI
OR
SI
OR
SI
OR
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
DI4
DO4
DI5
DO5
DI6
DO6
DI7
DO7
DI8 MR DO8
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
DI4
DO4
DI5
DO5
DI6
DO6
DI7
DO7
DI8 MR DO8
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
DI4
DO4
DI5
DO5
DI6
DO6
DI7
DO7
DI8 MR DO8
MR
C408A–21
Figure 5. Depth and Width Expansion[23,24,25,26,27].
Notes:
22. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the
devices.
23. When the memory is empty the last word read will remain on the outputs until the master reset is strobed or a new data word falls through to the output.
24. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until
the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.
25. If SO is held HIGH while the memory is empty and a word is written into the input, that word will fall through the memory to the output. OR will go HIGH for
one internal cycle (at least tPOR) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will
line up behind the first word and will not appear on the outputs until SO has been brought LOW.
26. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH, and OR goes LOW.
27. FIFOs are expandable in depth and width. However, in forming wider words, two external gates are required to generate composite input ready and output
ready flags. This need is due to the variation of delays of the FIFOs
28. Because the data throughput in the cascade interface is dependent on the inverter delay, it is recommended that the fastest available inverter be used.
29. Transmission of data packets assumes that up to the maximum cumulative capacity of the FIFOs is shifted in without simultaneous shift out clock occurring.
The complement of this holds when data is shifted out as a packet.
10
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