CY7C1355C-100AC Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción

Fabricante

CY7C1355C-100AC

9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1355C

CY7C1357C

Pin Definitions (continued)

Name

I/O

TDO

JTAG serial output

Synchronous

TDI

TMS

JTAG serial

input

Synchronous

JTAG serial

input

Synchronous

Description

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If

the JTAG feature is not being utilized, this pin should be left unconnected. This pin

is not available on TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

feature is not being utilized, this pin can be left floating or connected to VDD through

a pull up resistor. This pin is not available on TQFP packages.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG

feature is not being utilized, this pin can be disconnected or connected to VDD. This

pin is not available on TQFP packages.

TCK

NC

VSS/DNU

JTAG-Clock

-

Ground/DNU

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin

must be connected to VSS. This pin is not available on TQFP packages.

No Connects. Not internally connected to the die.

18M,36M, 72M, 144M and 288M are address expansion pins and are not internally

connected to the die.

This pin can be connected to Ground or should be left floating.

Document #: 38-05539 Rev. **

Page 8 of 33

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