CY7C1351G Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1351G Datasheet PDF : 14 Pages
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CY7C1351G
Truth Table [2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
NOP/DUMMY READ (Begin Burst)
DUMMY READ (Continue Burst)
WRITE Cycle (Begin Burst)
WRITE Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Address
Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
None H X X L
L
X X X L L->H
DQ
Tri-State
None X X H L
L
X X X L L->H Tri-State
None X L X L
L
X X X L L->H Tri-State
None X X X L H
X X X L L->H Tri-State
External L H L L
L
H X L L L->H Data Out (Q)
Next X X X L H
X X L L L->H Data Out (Q)
External L H L L
L
H X H L L->H Tri-State
Next
X XXL
H
X X H L L->H Tri-State
External L H L L
L
L L X L L->H Data In (D)
Next X X X L H
X L X L L->H Data In (D)
None L H L L
L
L H X L L->H Tri-State
Next
X XXL
H
X H X L L->H Tri-State
Current X X X L
X
X X X H L->H
–
None X X X H X
X X X X X Tri-State
Partial Truth Table for Read/Write [2, 3, 9]
Function
Read
Read
Write – No bytes written
Write Byte A – (DQA and DQPA)
Write Byte B – (DQB and DQPB)
Write Byte C – (DQC and DQPC)
Write Byte D – (DQD and DQPD)
Write All Bytes
WE
BWA
BWB
BWC
BWD
H
X
X
X
X
H
X
X
X
X
L
H
H
H
H
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
L
L
L
L
Notes:
2. X = Don’t Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BWX, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQP[A:D] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = tri-state when
OE is inactive or when the device is deselected, and DQs and DQP[A:D] = data when OE is active.
9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document #: 38-05513 Rev. *D
Page 6 of 14
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