CY7C1351G Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1351G Datasheet PDF : 14 Pages
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CY7C1351G
Pin Configurations (continued)
119-Ball BGA Pinout
1
2
3
4
5
6
7
A
VDDQ
A
B NC/576M CE2
C NC/1G
A
D
DQC DQPC
E
DQC
DQC
F
VDDQ
DQC
G
DQC
DQC
H
DQC
DQC
J
VDDQ
VDD
K
DQD
DQD
L
DQD
DQD
M
VDDQ
DQD
N
DQD
DQD
A
A
A
VSS
VSS
VSS
BWC
VSS
VSS
VSS
BWD
VSS
VSS
NC/18M
ADV/LD
VDD
NC
CE1
OE
NC/9M
WE
VDD
CLK
NC
CEN
A1
A
A
A
VSS
VSS
VSS
BWB
VSS
VSS
VSS
BWA
VSS
VSS
A
CE3
A
DQPB
DQB
DQB
DQB
DQB
VDD
DQA
DQA
DQA
DQA
VDDQ
NC
NC
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
P
DQD DQPD
VSS
A0
R NC/144M A
MODE
VDD
T
NC NC/72M A
A
VSS
DQPA
DQA
NC
A NC/288M
A NC/36M ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Pin Definitions
Name
A0, A1, A
BW[A:D]
WE
ADV/LD
CLK
CE1
CE2
CE3
OE
CEN
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
Description
Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
of the CLK. A[1:0] are fed to the two-bit burst counter.
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on
the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2, and CE3 to select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins.
OE is masked during the data portion of a write sequence, during the first clock when emerging
from a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
Document #: 38-05513 Rev. *D
Page 3 of 14
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