CY7C1351G Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY7C1351G

4-Mbit (128K x 36) Flow-through SRAM with NoBL™ Architecture

Cypress Semiconductor 

CY7C1351G

Switching Waveforms (continued)

NOP, STALL and DESELECT Cycles[19, 20, 22]

1

2

3

4

CLK

CEN

CE

ADV/LD

WE

BW[A:D]

ADDRESS

A1

A2

A3

DQ

COMMAND

WRITE

D(A1)

D(A1)

READ

Q(A2)

Q(A2)

STALL

READ

Q(A3)

5

6

A4

Q(A3)

WRITE

D(A4)

STALL

7

8

9

10

D(A4)

NOP

A5

tCHZ

Q(A5)

tDOH

READ

Q(A5)

DESELECT CONTINUE

DESELECT

ZZ Mode Timing[23,24]

CLK

ZZ

t ZZ

t ZZI

DON’T CARE

UNDEFINED

t ZZREC

I SUPPLY

ALL INPUTS

(except ZZ)

I DDZZ

t RZZI

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes:

22. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.

23. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.

24. DQs are in high-Z when exiting ZZ sleep mode.

Document #: 38-05513 Rev. *D

Page 11 of 14

[+] Feedback

Share Link: