CY7C1347G Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1347G Datasheet PDF : 21 Pages
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CY7C1347G
Pin Definitions (continued)
Name
MODE
IO
Input-
Static
NC, NC/9M,
–
NC/18M, NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M, NC/1G
Description
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ
or left floating selects interleaved burst sequence. This is a strap pin and must remain static
during device operation. Mode pin has an internal pull up.
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M,
NC/144M, NC/288M, NC/576M, and NC/1G are address expansion pins that are not inter-
nally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 2.6 ns (250
MHz device).
The CY7C1347G supports secondary cache in systems using
either a linear or interleaved burst sequence. The linear burst
sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is deter-
mined by sampling the MODE input. Accesses can be initiated
with either the Address Strobe from Processor (ADSP) or the
Address Strobe from Controller (ADSC). Address
advancement through the burst sequence is controlled by the
ADV input. A two-bit on-chip wraparound burst counter
captures the first address in a burst sequence and automati-
cally increments the address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
is HIGH. The address presented to the address inputs (A[16:0])
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corre-
sponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the Output Register and onto
the data bus within 2.6 ns (250 MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always tri-stated during the first cycle of the access. After the
first cycle of the access, the outputs are controlled by the OE
signal. Consecutive single read cycles are supported. After the
SRAM is deselected at clock rise by the chip select and either
ADSP or ADSC signals, its output tri-states immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted active. The address presented
to A[16:0] is loaded into the Address Register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW[A:D]) and ADV inputs are
ignored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs and DQPs inputs is written into the
corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW[A:D] signals. The CY7C1347G provides byte write
capability that is described in “Partial Truth Table for
Read/Write” on page 9. Asserting the Byte Write Enable input
(BWE) with the selected Byte Write (BW[A:D]) input selectively
writes to only the desired bytes.
Bytes not selected during a byte write operation remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347G is a common IO device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so tri-states the output
drivers. As a safety precaution, DQs and DQPs are automati-
cally tri-stated whenever a write cycle is detected, regardless
of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW[A:D]) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A[16:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is
conducted, the data presented to the DQs and DQPs is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1347G is a common IO device, the Output
Enable (OE) must be deasserted HIGH before presenting data
Document #: 38-05516 Rev. *E
Page 6 of 21
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