CY7C1347F Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1347F Datasheet PDF : 19 Pages
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CY7C1347F
Maximum Ratings
Current into Outputs (LOW)......................................... 20 mA
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Ambient
Range Temperature
VDD
VDDQ
DC Voltage Applied to Outputs
in High-Z State ........................................... −0.5V to VDD + 0.5V
DC Input Voltage ....................................... −0.5V to VDD + 0.5V
Com’l
Ind’l
0°C to +70°C 3.3V −5%/+10%
–40°C to +85°C
2.5V −5%
to VDD
Electrical Characteristics Over the Operating Range [8, 9]
Parameter
Description
Test Conditions
Min.
VDD
VDDQ
VOH
VOL
VIH
VIL
IX
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[8]
Input LOW Voltage[8]
Input Load Current ex-
cept ZZ and MODE
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA
VDDQ = 3.3V
VDDQ = 2.5V
VDDQ = 3.3V
VDDQ = 2.5V
GND ≤ VI ≤ VDDQ
3.135
2.375
2.4
2.0
2.0
1.7
–0.3
–0.3
−5
Input Current of MODE Input = VSS
−30
Input = VDDQ
Input Current of ZZ
Input = VSS
−5
Input = VDDQ
IOZ
Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled
−5
IDD
VDD Operating Supply VDD = Max., IOUT = 0 mA,
4-ns cycle, 250 MHz
Current
f = fMAX = 1/tCYC
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
ISB1
Automatic CE
Max. VDD, Device Deselected, 4-ns cycle, 250 MHz
Power-down
Current—TTL Inputs
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
4.4-ns cycle, 225 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
ISB2
Automatic CE
Max. VDD, Device Deselected, All speeds
Power-down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f
Current—CMOS Inputs = 0
Notes:
8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2).
9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD
Max.
3.6
VDD
0.4
0.7
VDD + 0.3V
VDD + 0.3V
0.8
0.7
5
5
30
5
325
290
265
240
225
120
115
110
100
90
40
Unit
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Document #: 38-05213 Rev. *D
Page 8 of 19
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