CY7C1347F Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1347F Datasheet PDF : 19 Pages
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CY7C1347F
Switching Characteristics Over the Operating Range[15, 16]
-250
-225
-200
-166
-133
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
tPOWER
VDD(min.) to
read or write
the
[11]
first
access
1
1
1
1
1
ms
tCYC
Clock Cycle Time
4.0
4.4
5.0
6.0
7.5
ns
tCH
Clock HIGH
1.7
2.0
2.0
2.5
3.0
ns
tCL
Clock LOW
1.7
2.0
2.0
2.5
3.0
ns
tAS
Address Set-up Before CLK 0.8
1.2
1.2
1.5
1.5
ns
Rise
tAH
Address Hold After CLK Rise 0.4
0.5
0.5
0.5
0.5
ns
tCO
Data Output Valid After CLK
2.6
2.6
2.8
3.5
4.0 ns
Rise
tDOH
Data Output Hold After CLK 1.0
1.0
1.0
2.0
2.0
ns
Rise
tWES
GW, BWS[3:0] Set-up Before 0.8
1.2
1.2
1.5
1.5
ns
CLK Rise
tWEH
GW, BWS[3:0] Hold After CLK 0.4
0.5
0.5
0.5
0.5
ns
Rise
tALS
ADV/LD Set-up Before CLK 0.8
1.2
1.2
1.5
1.5
ns
Rise
tALH
ADV/LD Hold after CLK Rise 0.4
0.5
0.5
0.5
0.5
ns
tDS
Data Input Set-up Before CLK 0.8
1.2
1.2
1.5
1.5
ns
Rise
tDH
Data Input Hold After CLK
0.4
0.5
0.5
0.5
0.5
ns
Rise
tCES
Chip Enable Set-up Before 0.8
1.2
1.2
1.5
1.5
ns
CLK Rise
tCEH
tCHZ
tCLZ
tEOHZ
Chip Enable Hold After CLK 0.4
0.5
0.5
0.5
0.5
ns
Rise
Clock to High-Z[12, 13, 14]
2.6
2.6
2.8
3.5
4.0 ns
Clock to Low-Z[12, 13, 14]
0
0
0
0
0
ns
OE HIGH to Output
High-Z[12, 13, 14]
2.6
2.6
2.8
3.5
4.0 ns
tEOLZ
OE LOW to Output
Low-Z[12, 13, 14]
0
0
0
0
0
ns
tEOV
OE LOW to Output Valid
2.6
2.6
2.8
3.5
4.5 ns
Notes:
11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation
can be initiated.
12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing references level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V on all data sheets.
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05213 Rev. *D
Page 10 of 19
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