CY7C1347D-166AC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1347D-166AC Datasheet PDF : 21 Pages
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CY7C1347D
CY7C1347D Pin Descriptions (continued)
BGA Pins
2U
QFP Pins
39
Name
TDI
Type
Input
3U
43
TCK
Input
5U
1B, 7B, 1C, 7C, 4D,
3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 6U
42
14, 16, 66
TDO
NC
Output
–
Description
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to VCC.
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to VSS
or VCC.
IEEE 1149.1 test output. LVTTL-level output. If JTAG feature is
not utilized, this pin should be disconnected.
No Connect: These signals are not internally connected.
Burst Address Table (MODE = NC/VCC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
A...A00
A...A01
A...A10
A...A11
Second
Address
(internal)
A...A01
A...A10
A...A11
A...A00
Third
Address
(internal)
A...A10
A...A11
A...A00
A...A01
Fourth
Address
(internal)
A...A11
A...A00
A...A01
A...A10
Truth Table [2, 3, 4, 5, 6, 7]
Operation
Address
Used CE CE2 CE2 ADSP ADSC ADV Write OE CLK DQ
Deselected Cycle, Power-down None H X X
X
L
X
X
X L-H High-Z
Deselected Cycle, Power-down None L X L
L
X
X
X
X L-H High-Z
Deselected Cycle, Power-down None L H X
L
X
X
X
X L-H High-Z
Deselected Cycle, Power-down None L X L
H
L
X
X
X L-H High-Z
Deselected Cycle, Power-down None L H X
H
L
X
X
X L-H High-Z
Read Cycle, Begin Burst
External L L H
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External L L H
L
X
X
X
H L-H High-Z
Write Cycle, Begin Burst
External L L H
H
L
X
L
X L-H
D
Read Cycle, Begin Burst
External L L H
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External L L H
H
L
X
H
H L-H High-Z
Read Cycle, Continue Burst
Next X X X
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next X X X
H
H
L
H
H L-H High-Z
Read Cycle, Continue Burst
Next H X X
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next H X X
X
H
L
H
H L-H High-Z
Write Cycle, Continue Burst
Next X X X
H
H
L
L
X L-H
D
Write Cycle, Continue Burst
Next H X X
X
H
L
L
X L-H
D
Read Cycle, Suspend Burst
Current X X X
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current X X X
H
H
H
H
H L-H High-Z
Notes:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
Write = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. Write = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH. BWa enables write to
DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
3. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout
the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
7. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the
CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification.
Document #: 38-05022 Rev. *D
Page 5 of 21
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