CY7C1347D-250 Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
CY7C1347D-250 Datasheet PDF : 21 Pages
| |||
CY7C1347D
Pin Configurations (continued)
119-Ball BGA
Top View
1
2
3
4
5
6
7
A
VCCQ
A
B
NC
CE2
A
ADSP
A
A
ADSC
A
A
CE2
VCCQ
NC
C
NC
A
A
VCC
A
A
NC
D
DQc
DQc
VSS
NC
VSS
DQb
DQb
E
DQc
DQc
VSS
CE
VSS
DQb
DQb
F
VCCQ
DQc
VSS
OE
VSS
DQb
VCCQ
G
DQc
DQc
BWc
ADV
BWb
DQb
DQb
H
DQc
DQc
VSS
GW
VSS
DQb
DQb
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VCCQ
DQd
VSS
BWE
VSS
DQa
VCCQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQd
VSS
A0
VSS
DQa
DQa
R
NC
A
MODE
VCC
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
CY7C1347D Pin Descriptions
BGA Pins
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R,
3T, 4T, 5T
5L
5G
3G
3L
QFP Pins
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47,
48, 49, 50
93
94
95
96
Name
A0
A1
A
BWa
BWb
BWc
BWd
4M
87
BWE
4H
88
GW
4K
89
CLK
4E
98
CE
6B
92
CE2
2U
38
TMS
Type
Input-
Synchronous
Description
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input
Byte Write: A byte write is LOW for a Write cycle and HIGH for
a Read cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE being
LOW.
Write Enable: This active LOW input gates byte write operations
and must meet the set-up and hold times around the rising edge
of CLK.
Global Write: This active LOW input allows a full 36-bit Write to
occur independent of the BWE and BWn lines and must meet
the set-up and hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet set-up and hold times around
the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the device
and to gate ADSP.
Chip Enable: This active LOW input is used to enable the
device.
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to VSS.
Document #: 38-05022 Rev. *D
Page 4 of 21
Share Link: 