CY7C1347B-133AC Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY7C1347B-133AC

128K x 36 Synchronous-Pipelined Cache RAM

Cypress Semiconductor 

CY7C1347B

Interleaved Burst Sequence

First

Address

A[1:0]

00

01

10

11

Second

Address

A[1:0]

01

00

11

10

Third

Address

A[1:0]

10

11

00

01

Fourth

Address

A[1:0]

11

10

01

00

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ plac-

es the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered

valid nor is the completion of the operation guaranteed. The

device must be deselected prior to entering the “sleep” mode.

CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the

duration of tZZREC after the ZZ input returns LOW.

Linear Burst Sequence

First

Address

A[1:0]

00

01

10

11

Second

Address

A[1:0]

01

10

11

00

Third

Address

A[1:0]

10

11

00

01

Fourth

Address

A[1:0]

11

00

01

10

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

IDDZZ

Snooze mode

standby current

ZZ > VDD − 0.2V

10

mA

tZZS

Device operation to ZZ > VDD − 0.2V

ZZ

2tCYC

ns

tZZREC

ZZ recovery time

ZZ < 0.2V

2tCYC

ns

.

6

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