CY7C1347B-133BGC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1347B-133BGC Datasheet PDF : 17 Pages
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CY7C1347B
Pin Definitions
Name
A[16:0]
BW[3:0]
GW
BWE
CLK
CE1
CE2
CE3
OE
ADV
ADSP
ADSC
ZZ
DQ[31:0]
DP[3:0]
VDD
VSS
VDDQ
VSSQ
MODE
NC
I/O
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
I/O-
Synchronous
Power Supply
Ground
I/O Power
Supply
I/O Ground
Input-
Static
Description
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the
2-bit counter.
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW[3:0] and BWE).
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.
Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically incre-
ments the address in a burst cycle.
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[16:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted
HIGH.
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[16:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition
with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin
has an internal pull-down.
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by
OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[31:0] and DP[3:0] are
placed in a three-state condition.
Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
Ground for the core of the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.
Ground for the I/O circuitry. Should be connected to ground of the system.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left
floating selects interleaved burst sequence. This is a strap pin and should remain static during
device operation. Mode Pin has an internal pull-up.
No Connects.
4
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