CY7C1345G Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
CY7C1345G Datasheet PDF : 17 Pages
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PRELIMINARY
Pin Configurations (continued)
1
A
VDDQ
B
NC
C
NC
D
DQC
E
DQC
F
VDDQ
G
DQC
H
DQC
J
VDDQ
K
DQD
L
DQD
M
VDDQ
N
DQD
P
DQD
R
NC
T
NC
U
VDDQ
2
A
CE2
A
DQPC
DQC
DQC
DQC
DQC
VDD
DQD
DQD
DQD
DQD
DQPD
A
NC
NC
119-Ball BGA
3
A
A
A
VSS
VSS
VSS
BWC
VSS
NC
VSS
BWD
VSS
VSS
VSS
MODE
A
NC
4
ADSP
ADSC
VDD
NC
CE1
OE
ADV
GW
VDD
CLK
NC
BWE
A1
A0
VDD
A
NC
5
A
A
A
VSS
VSS
VSS
BWB
VSS
NC
VSS
BWA
VSS
VSS
VSS
NC
A
NC
CY7C1345G
6
A
CE3
A
DQPB
DQB
DQB
DQB
DQB
VDD
DQA
DQA
DQA
DQA
DQPA
A
NC
NC
7
VDDQ
NC
NC
DQB
DQB
VDDQ
DQB
DQB
VDDQ
DQA
DQA
VDDQ
DQA
DQA
NC
ZZ
VDDQ
Pin Definitions
Name
A0, A1, A
BWA,BWB
BWC,BWD
GW
BWE
CLK
CE1
CE2
CE3
OE
ADV
I/O
Description
Input- Address Inputs used to select one of the 128K address locations. Sampled at the rising edge
Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed
the 2-bit counter.
Input- Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
Input- Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
Input- Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input- Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only
when a new external address is loaded.
Input- Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
Synchronous CE1 and CE3 to select/deselect the device.CE2 is sampled only when a new external address is
loaded.
Input- Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded.
Input- Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When
Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as
input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected
state.
Input- Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically
Synchronous increments the address in a burst cycle.
Document #: 38-05517 Rev. *A
Page 3 of 17
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