CY7C1340G-133AXC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1340G-133AXC Datasheet PDF : 16 Pages
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CY7C1340G
Switching Characteristics Over the Operating Range [12, 13, 14, 15, 16]
Parameter
tPOWER
Clock
tCYC
tCH
tCL
Output Times
tCO
tDOH
tCLZ
tCHZ
tOEV
tOELZ
tOEHZ
Set-up Times
tAS
tADS
tADVS
tWES
tDS
tCES
Hold Times
tAH
tADH
tADVH
tWEH
tDH
tCEH
Description
VDD(Typical) to the first Access[11]
Clock Cycle Time
Clock HIGH
Clock LOW
–250
–200
–166
–133
Min. Max. Min. Max. Min. Max. Min. Max. Unit
1.0
1.0
1.0
1.0
ms
4.0
5.0
6.0
7.5
ns
1.7
2.0
2.5
3.0
ns
1.7
2.0
2.5
3.0
ns
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z[12, 13, 14]
Clock to High-Z[12, 13, 14]
OE LOW to Output Valid
OE LOW to Output Low-Z[12, 13, 14]
OE HIGH to Output High-Z[12, 13, 14]
2.6
2.8
3.5
4.0 ns
1.0
1.0
1.5
1.5
ns
0
0
0
0
ns
2.6
2.8
3.5
4.0 ns
2.6
2.8
3.5
4.0 ns
0
0
0
0
ns
2.6
2.8
3.5
4.0 ns
Address Set-up Before CLK Rise
1.2
1.2
1.5
1.5
ns
ADSC, ADSP Set-up Before CLK Rise 1.2
1.2
1.5
1.5
ns
ADV Set-up Before CLK Rise
1.2
1.2
1.5
1.5
ns
GW, BWE, BWX Set-up Before CLK Rise 1.2
1.2
1.5
1.5
ns
Data Input Set-up Before CLK Rise
1.2
1.2
1.5
1.5
ns
Chip Enable Set-up Before CLK Rise
1.2
1.2
1.5
1.5
ns
Address Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
ADSP, ADSC Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
ADV Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
GW, BWE, BWX Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
Data Input Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
Chip Enable Hold After CLK Rise
0.3
0.5
0.5
0.5
ns
Notes:
11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation
can be initiated.
12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
14. This parameter is sampled and not 100% tested.
15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.
16. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05522 Rev. *D
Page 10 of 16
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