HCF40100M013TR Ver la hoja de datos (PDF) - STMicroelectronics
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HCF40100M013TR Datasheet PDF : 11 Pages
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HCF40100B
32-STAGE STATIC LEFT/RIGHT SHIFT REGISTER
s FULLY STATIC OPERATION
s SHIFT LEFT/SHIFT RIGHT CAPABILITY
s MULTIPLE PACKAGE CASCADING
s RECIRCULATE CAPABILITY
s LIFO OR FIFO CAPABILITY
s STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
s QUIESCENT CURRENT SPECIF. UP TO 20V
s 5V, 10V AND 15V PARAMETRIC RATINGS
s INPUT LEAKAGE CURRENT
II = 100nA (MAX) AT VDD = 18V TA = 25°C
s 100% TESTED FOR QUIESCENT CURRENT
s MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
DESCRIPTION
HCF40100B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40100B is a 32-stage shift register containing
32 D-Type master slave flip-flops. The data
present at the SHIFT RIGHT INPUT is
synchronously transferred into the first register
stage with the positive CLOCK edge, provided the
LEFT/RIGHT CONTROL is at a low level, the
RECIRCULATE CONTROL is at a high level, and
the CLOCK INHIBIT is low. If the LEFT/RIGHT
control and the RECIRCULATE CONTROL are
both at a high level, data at the SHIFT LEFT
INPUT is synchronously transferred into the 32nd
PIN CONNECTION
DIP
SOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
HCF40100BEY
HCF40100BM1
T&R
HCF40100M013TR
register stage with the positive CLOCK transition,
provided the CLOCK INHIBIT is low. The state of
the LEFT/RIGHT CONTROL, RECIRCULATE
CONTROL, and CLOCK INHIBIT should not be
changed when the CLOCK is high. Data is
synchronously shifted one stage left or one stage
right depending on the state of the LEFT/RIGHT
CONTROL, with the positive CLOCK edge. Data
clocked into the first of 32 register states is
available at the SHIFT LEFT or SHIFT RIGHT
OUTPUT respectively, on the next negative
CLOCK transition (see Data Transfer Table). No
shifting occurs on the positive CLOCK edge if the
CLOCK INHIBIT line is at a high level. With the
RECIRCULATE CONTROL low, data in the 32nd
stage is shifted into the first stage when the LEFT/
RIGHT CONTROL is low and from the 1st stage to
the 32nd stage when the LEFT/RIGHT CONTROL
is high.
September 2002
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