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Número de pieza
componentes Descripción
CY7C1328G Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
CY7C1328G
4-Mbit (256K x 18) Pipelined DCD Sync SRAM
Cypress Semiconductor
CY7C1328G Datasheet PDF : 16 Pages
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CY7C1328G
Switching Waveforms
Read Timing
[16]
CLK
ADSP
ADSC
ADDRESS
GW, BWE,BW
[A:B]
CE
ADV
OE
Data Out (DQ)
tCYC
tCH tCL
tADS tADH
tADS tADH
tAS tAH
A1
A2
tWES tWEH
tCES tCEH
A3
Burst continued with
new base address
Deselect
cycle
tADVS tADVH
ADV suspends burst
t
CLZ
High-Z
tCO
tOEHZ
Q(A1)
Single READ
tOEV
tOELZ
tCO
tDOH
Q(A2) Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
BURST READ
tCHZ
Q(A2) Q(A2 + 1)
Q(A3)
Burst wraps around
to its initial state
DON’T CARE
UNDEFINED
Note:
16. On this diagram, when CE is LOW: CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH: CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
Document #: 38-05523 Rev. *E
Page 11 of 16
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