AD5533(Rev0) Ver la hoja de datos (PDF) - Analog Devices
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AD5533 Datasheet PDF : 16 Pages
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AD5533
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Parameter1, 2
Limit at TMIN, TMAX
(A Version)
Unit
t1
0
t2
0
t3
50
t4
50
t5
20
t6
0
ns min
ns min
ns min
ns min
ns min
ns min
NOTES
1See Interface Timing Diagram.
2Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACE
Parameter1, 2
Limit at TMIN, TMAX
(A Version)
Unit
fCLKIN
20
t1
20
t2
20
t3
10
t4
50
t5
10
t6
5
t7
5
t83
20
t93
60
t10
400
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
NOTES
1See Serial Interface Timing Diagrams.
2Guaranteed by design and characterization, not production tested.
3These numbers are measured with the load circuit of Figure 2.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAM
CS
WR
A4–A0, CAL,
OFFS SEL
Figure 1. Parallel Write (SHA Mode Only)
Conditions/Comments
CS to WR Setup Time
CS to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
A4–A0, CAL, OFFS_SEL to WR Setup Time
A4–A0, CAL, OFFS_SEL to WR Hold Time
Conditions/Comments
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
DIN Setup Time
DIN Hold Time
SYNC Falling Edge to SCLK Rising Edge Setup Time
SCLK Rising Edge to DOUT Valid
SCLK Falling Edge to DOUT High Impedance
10th SCLK Falling Edge to SYNC Falling Edge for Readback
TO
OUTPUT
PIN
200A
IOL
CL
50pF
200A
IOH
1.6V
Figure 2. Load Circuit for DOUT Timing Specifications
–4–
REV. 0
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