HV623PG Ver la hoja de datos (PDF) - Supertex Inc
Número de pieza
componentes Descripción
Fabricante
HV623PG Datasheet PDF : 10 Pages
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Pin Definitions
Pin #
Name
Function
– OBSOLETE –
30-36
D1-D7
Inputs for binary-format parallel data.
HV623
26
SC (Shift Clock) Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock
rate (data rate = 8MHz max if clock rate = 4.0MHz max).
22
CSI (Chip Input pin for the chip select pulse (when DIR is high).
Select Input) Output pin for the chip select pulse (when DIR is low).
43
CSO (Chip Input pin for the chip select pulse (when DIR is low).
Select Output) Output pin for the chip select pulse (when DIR is high).
40
LC
Input for a pulse whose rising edge causes data from the input latches to enter the comparator latches,
(Load Count) and whose falling edge initiates the conversion of this binary data to an output level (D-to-A).
Also, the HVOUT will clear to zero after the load count is initiated.
42
CC (Count Clock) Input to the count clock generator whose increments are compared to the data in the comparator latches.
18, 47
VR
High-voltage ramp input for charging the output stage hold capacitors (CH).
This input can be linear or non-linear as desired.
28
27, 38
DIR
LVGND
When this pin is connected to VDD, input data is shifted in ascending order,
i.e., corresponding to HVOUT1 to HVOUT32. When connected to LVGND, input data is shifted
in descending order, i.e., corresponding to HVOUT32 to HVOUT1.
This is ground for the logic section.
HVGND and LVGND should be connected together externally.
17, 48
HVGND
This is ground for the high-voltage (output) section.
HVGND and LVGND should be connected together externally.
19, 45
1-16
49-64
21
29
24
VPP
HVOUT1-
HVOUT32
VDD (Analog)
VDD (Digital)
VCTL
This input biases the output source followers.
High-voltage outputs.
Low-voltage analog supply voltage.
Low-voltage digital supply voltage.
Voltage supply pin to prevent output voltage from being affected by its adjacent outputs (VCTL = 2V for a
particular panel). The combination of VCTL and RCTL will reduce the output voltage variation to less than
±0.2V of delta voltage between high voltage outputs of the same level at all gray levels.
25
RCTL
Current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs
(RCTL = 56KΩ for a particular panel). See VCTL function above.
Input and Output Equivalent Circuits
VDD
VDD
Input
GND
(Logic)
Logic Inputs
Data Out
GND
(Logic)
Logic Data Output
5
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