HV623 Ver la hoja de datos (PDF) - Supertex Inc
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HV623 Datasheet PDF : 10 Pages
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HV623
Theory of Operation
The HV623 has two primary functions:
1) Loading data from the data bus and,
2) Gray-shade conversion
(converting latched data to output voltages).
Since the device was developed initially for flat panel displays, the
operation will be described in terms that pertain to that technol-
ogy. As shown by the Typical Drive Scheme, several HV623
packages are mounted at the top and bottom of a display panel.
Data exists on a 7-bit bus (adjacent PC board traces) at top and
bottom. The D1 through D7 inputs of each chip take data from the
bus when either a CSI or CSO pulse is present at the chip. These
pulses therefore act as a combination CHIP SELECT and LOCA-
TION STROBE. Because of the way the chip HVOUT pins are
sequenced, data on the bus at the bottom of the display panel will
be entered into the left-most chip as HVOUT1, HVOUT2, etc. up to
HVOUT32. The CSI pulse will accomplish this with DIR = High.
Loading Data from Data Bus
Here is the full data-entry sequence:
When data has been loaded into all 32 outputs of all chips (top and
bottom of the display panel), the load count pin is pulsed. On its
rising transition, all output levels are reset to zero and all the data
in the input latches is transferred to a like number of comparator
latches, (thus leaving the data latches ready to receive new data
during the following operations). After the transfer, the load count
pin is brought low. This transition begins the events that convert
the binary data into a gray-shade level.
Gray-shade Conversion
1) The COUNT CLOCK is started. An external signal is applied
to the COUNT CLOCK pin, causing the counter on each chip
to increment from binary 000 0000 to 111 1111 (0 to 127).
2) At the same time, the VR voltage is applied to all chips, via
charging transistors, causing the HOLD CAPACITOR (CH) on
each output to experience a rise in voltage.
3) The logic control compares the count in the comparator latch
to the count clock. The gate voltage of Q1 and the output
voltage HVOUT will ramp up at the same rate as VR.
4) Once VR has reached the maximum voltage, then all the pixels
will be at the final value. (See Output Gray Scale Voltage.)
1) The microcontroller puts data on the bus (7 bits)
2) To enter the data into the 32 sets of 7 latches on the first chip,
Output Voltage Variation
the shift clock rises. This positive transition is combined with
the CSI pulse and is generated only once to strobe the data into
the first set of latches. (These latches eventually send data to
the HVOUT1). The data on the bus then changes, the shift clock
falls, and this negative transition is combined with the CSI
pulse, which is now propagated internally, to strobe the new
data into the next set of 7 latches (which will end up as
HVOUT2). This internal CSI pulse therefore runs at twice the
shift clock rate.
3) When the last set of 7 latches in the first chip has been loaded
(HVOUT32), the CSI pulse leaves chip 1 and enters chip 2. The
exit pin is called CSO and the chip 2 entry pin is CSI . For chips
at the top of the panel things are reversed: DIR is low, entry pins
are CSO and exit pins are CSI , because the data-into-latches
sequence is in descending order, HVOUT32 down to HVOUT1.
The output voltage of the HV623 is determined by the logic and
the ramp voltage VR. It is possible that the output voltage may be
coupled to an unacceptable level due to its adjacent outputs
through the panel. In order to solve this problem, internal logic
(refer to Output Stage Detail) is integrated in the IC to minimize
the effect.
Two external pins VCTL and RCTL allow the feasibility to control the
current flowing through Q . The V pin is connected to a voltage
2
CTL
source and the RCTL pin is connected to ground through a resistor
(2V and 56KΩ are used for a particular panel). The internal bias
circuit will drive the resistor to a voltage level that is equal to the
VCTL voltage at steady state through an operational amplifier. The
current flowing through Q1 and Q2 will be limited to VCTRL/RCTRL.
This combination of VCTL and RCTL will reduce the output voltage
variation to less than ±0.2V of delta voltage for each gray shade,
4) The buses may of course be separate, and data can be strobed
independent of its adjacent output voltages.
in on an interleaved basis, etc., but those complications will be
left to systems designers.
– OBSOLETE –
©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited.
10
12/04/02
1235 Bordeaux Drive, Sunnyvale, CA 94089
TEL: (408) 744-0100 • FAX: (408) 222-4895
www.supertex.com
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