CY7C1339G(2004) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1339G Datasheet PDF : 17 Pages
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PRELIMINARY
CY7C1339G
Truth Table [ 2, 3, 4, 5, 6, 7]
Operation
Add. Used CE1 CE2 CE3 ZZ ADSP ADSC ADV WRITE OE CLK
DQ
Deselect Cycle, Power-down None
H X XL X
L
X
X
X L-H tri-state
Deselect Cycle, Power-down None
L L XL L
X
X
X
X L-H tri-state
Deselect Cycle, Power-down None
L X HL L
X
X
X
X L-H tri-state
Deselect Cycle, Power-down None
L L XL H
L
X
X
X L-H tri-state
Deselect Cycle, Power-down None
L X HL H
L
X
X
X L-H tri-state
Snooze Mode, Power-down None
X X XH X
X
X
X
X X tri-state
READ Cycle, Begin Burst
External L H L L L
X
X
X
L L-H
Q
READ Cycle, Begin Burst
External L H L L L
X
X
X
H L-H tri-state
WRITE Cycle, Begin Burst External L H L L H
L
X
L
X L-H
D
READ Cycle, Begin Burst
External L H L L H
L
X
H
L L-H
Q
READ Cycle, Begin Burst
External L H L L H
L
X
H H L-H tri-state
READ Cycle, Continue Burst Next
X X XL H
H
L
H
L L-H
Q
READ Cycle, Continue Burst Next
X X XL H
H
L
H H L-H tri-state
READ Cycle, Continue Burst Next
H X XL X
H
L
H
L L-H
Q
READ Cycle, Continue Burst Next
H X XL X
H
L
H H L-H tri-state
WRITE Cycle, Continue Burst Next
X X XL H
H
L
L
X L-H
D
WRITE Cycle, Continue Burst Next
H X XL X
H
L
L
X L-H
D
READ Cycle, Suspend Burst Current X X X L H
H
H
H
L L-H
Q
READ Cycle, Suspend Burst Current X X X L H
H
H
H H L-H tri-state
READ Cycle, Suspend Burst Current H X X L X
H
H
H
L L-H
Q
READ Cycle, Suspend Burst Current H X X L X
H
H
H H L-H tri-state
WRITE Cycle, Suspend Burst Current X X X L H
H
H
L
X L-H
D
WRITE Cycle, Suspend Burst Current H X X L X
H
H
L
X L-H
D
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals
(BWA, BWB, BWC, BWD), BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only 2 chip selects CE1 and CE2.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a
don't care for the remainder of the write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05520 Rev. *A
Page 6 of 17
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