CY7C1316AV18 Ver la hoja de datos (PDF) - Cypress Semiconductor
Número de pieza
componentes Descripción
Fabricante
CY7C1316AV18 Datasheet PDF : 20 Pages
| |||
CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied .. –55°C to +125°C
Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V
DC Applied to Outputs in High-Z......... –0.5V to VDDQ + 0.5V
DC Input Voltage[9].............................. –0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range[11]
DC Electrical Characteristics
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V
Latch-up Current..................................................... >200 mA
Operating Range
Range
Com’l
Ambient
Temperature
0°C to +70°C
VDD[10]
1.8 ± 0.1V
VDDQ[10]
1.4V to VDD
Parameter
Description
Test Conditions
Min.
VDD
VDDQ
VOH
VOL
VOH(LOW)
VOL(LOW)
VIH
VIL
VIN
IX
IOZ
VREF
IDD
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[9]
Input LOW Voltage[9, 14]
Clock Input Voltage
Input Load Current
Output Leakage Current
Input Reference Voltage[15]
VDD Operating Supply
1.7
1.4
Note 12
VDDQ/2 – 0.12
Note 13
VDDQ/2 – 0.12
IOH = –0.1 mA, Nominal Impedance VDDQ – 0.2
IOL = 0.1 mA, Nominal Impedance
VSS
VREF + 0.1
–0.3
–0.3
GND ≤ VI ≤ VDDQ
GND ≤ VI ≤ VDDQ, Output Disabled
Typical Value = 0.75V
–5
–5
0.68
VDD = Max., IOUT = 0 mA, 167 MHz
f = fMAX = 1/tCYC
200 MHz
250 MHz
ISB1
Automatic Power-down
Current
AC Input Requirements
Max. VDD, Both Ports 167 MHz
Deselected, VIN ≥ VIH or
VIN ≤ VIL f = fMAX =
1/tCYC, Inputs Static
200 MHz
250 MHz
Parameter
Description
Test Conditions
Min.
VIH
Input High (Logic 1) Voltage
VIL
Input Low (Logic 0) Voltage
VREF + 0.2
–
Capacitance[16]
Typ.
1.8
1.5
0.75
Typ.
–
–
Max.
Unit
1.9
V
VDD
V
VDDQ/2 + 0.12 V
VDDQ/2 + 0.12 V
VDDQ
V
0.2
V
VDDQ + 0.3 V
VREF – 0.1
V
VDD + 0.3
V
5
µA
5
µA
0.95
V
700
mA
750
mA
800
mA
450
mA
470
mA
490
mA
Max.
–
VREF – 0.2
Unit
V
V
Parameter
Description
Test Conditions
Max.
CIN
CCLK
CO
Input Capacitance
TA = 25°C, f = 1 MHz,
5
Clock Input Capacitance
VDD = 1.8V
6
Output Capacitance
VDDQ = 1.5V
7
Notes:
9. Overshoot: VIH(AC) < VDD+0.85V (Pulse width less than tTCYC/2); Undershoot VIL(AC) > −1.5V (Pulse width less than tTCYC/2).
10. Power-up: Assumes a linear ramp from 0V to VDD(Min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
11. All voltage referenced to ground.
12. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
13. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
14. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max.) = VREF – 0.2V.
15. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
16. Tested initially and after any design or process change that may affect these parameters.
Unit
pF
pF
pF
Document #: 38-05499 Rev. *B
Page 9 of 20
Share Link: 